Searched refs:divn_shift (Results 1 – 5 of 5) sorted by relevance
| /linux-4.1.27/drivers/clk/tegra/ |
| D | clk-tegra124.c | 163 .divn_shift = 8,
259 .divn_shift = 8,
333 .divn_shift = 8,
408 .divn_shift = 8,
449 .divn_shift = 8,
487 .divn_shift = 8,
514 .divn_shift = 8,
578 .divn_shift = 8,
696 .divn_shift = 8,
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| D | clk-pll.c | 203 #define divn_shift(p) (p)->params->div_nmp->divn_shift macro
207 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
215 .divn_shift = PLL_BASE_DIVN_SHIFT,
507 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
534 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
760 val |= sel.n << divn_shift(pll); in clk_plle_enable()
794 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1327 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1477 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1639 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
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| D | clk-tegra114.c | 181 .divn_shift = 8,
243 .divn_shift = 8,
315 .divn_shift = 8,
362 .divn_shift = 8,
490 .divn_shift = 8,
570 .divn_shift = 8,
598 .divn_shift = 8,
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| D | clk.h | 148 u8 divn_shift; member
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| D | clk-tegra30.c | 430 .divn_shift = 8,
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