| H A D | dib8000.c | 247 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) dib8000_write_word() function
399 dib8000_write_word(state, 298, nud); dib8000_set_acquisition_mode()
454 dib8000_write_word(state, 299, smo_mode); dib8000_set_output_mode()
455 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ dib8000_set_output_mode()
456 dib8000_write_word(state, 1286, outreg); dib8000_set_output_mode()
457 dib8000_write_word(state, 1291, sram); dib8000_set_output_mode()
469 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 dib8000_set_diversity_in()
470 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 dib8000_set_diversity_in()
472 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 dib8000_set_diversity_in()
473 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 dib8000_set_diversity_in()
479 dib8000_write_word(state, 270, 1); dib8000_set_diversity_in()
480 dib8000_write_word(state, 271, 0); dib8000_set_diversity_in()
483 dib8000_write_word(state, 270, 6); dib8000_set_diversity_in()
484 dib8000_write_word(state, 271, 6); dib8000_set_diversity_in()
487 dib8000_write_word(state, 270, 0); dib8000_set_diversity_in()
488 dib8000_write_word(state, 271, 1); dib8000_set_diversity_in()
494 dib8000_write_word(state, 903, tmp & ~(1 << 3)); dib8000_set_diversity_in()
496 dib8000_write_word(state, 903, tmp | (1 << 3)); dib8000_set_diversity_in()
535 dib8000_write_word(state, 774, reg_774); dib8000_set_power_mode()
536 dib8000_write_word(state, 775, reg_775); dib8000_set_power_mode()
537 dib8000_write_word(state, 776, reg_776); dib8000_set_power_mode()
538 dib8000_write_word(state, 900, reg_900); dib8000_set_power_mode()
539 dib8000_write_word(state, 1280, reg_1280); dib8000_set_power_mode()
552 ret |= dib8000_write_word(state, 908, reg_908); dib8000_set_adc_state()
557 dib8000_write_word(state, 1925, reg | dib8000_set_adc_state()
564 dib8000_write_word(state, 1925, reg & ~(1<<4)); dib8000_set_adc_state()
570 dib8000_write_word(state, 921, reg | (1 << 14) dib8000_set_adc_state()
579 dib8000_write_word(state, 1925, dib8000_set_adc_state()
607 ret |= dib8000_write_word(state, 907, reg_907); dib8000_set_adc_state()
608 ret |= dib8000_write_word(state, 908, reg_908); dib8000_set_adc_state()
629 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); dib8000_set_bandwidth()
630 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); dib8000_set_bandwidth()
640 dib8000_write_word(state, 922, (sad_sel << 2)); dib8000_sad_calib()
641 dib8000_write_word(state, 923, 2048); dib8000_sad_calib()
643 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1); dib8000_sad_calib()
644 dib8000_write_word(state, 922, (sad_sel << 2)); dib8000_sad_calib()
647 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); dib8000_sad_calib()
648 dib8000_write_word(state, 924, 776); dib8000_sad_calib()
651 dib8000_write_word(state, 923, (1 << 0)); dib8000_sad_calib()
652 dib8000_write_word(state, 923, (0 << 0)); dib8000_sad_calib()
665 return dib8000_write_word(state, 106, value); dib8000_set_wbd_ref()
672 dib8000_write_word(state, 23, dib8000_reset_pll_common()
674 dib8000_write_word(state, 24, dib8000_reset_pll_common()
677 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); dib8000_reset_pll_common()
678 dib8000_write_word(state, 24, dib8000_reset_pll_common()
681 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); dib8000_reset_pll_common()
682 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); dib8000_reset_pll_common()
683 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); dib8000_reset_pll_common()
686 dib8000_write_word(state, 922, bw->sad_cfg); dib8000_reset_pll_common()
695 dib8000_write_word(state, 901, dib8000_reset_pll()
703 dib8000_write_word(state, 902, clk_cfg1); dib8000_reset_pll()
705 dib8000_write_word(state, 902, clk_cfg1); dib8000_reset_pll()
711 dib8000_write_word(state, 904, dib8000_reset_pll()
716 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | dib8000_reset_pll()
721 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | dib8000_reset_pll()
725 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | dib8000_reset_pll()
730 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); dib8000_reset_pll()
733 dib8000_write_word(state, 1858, reg | 1); dib8000_reset_pll()
735 dib8000_write_word(state, 904, (pll->modulo << 8)); dib8000_reset_pll()
762 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15)); dib8000_update_pll()
764 dib8000_write_word(state, 1856, reg_1856 | dib8000_update_pll()
776 dib8000_write_word(state, 23, dib8000_update_pll()
778 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); dib8000_update_pll()
780 dib8000_write_word(state, 1857, reg_1857 | (1 << 15)); dib8000_update_pll()
799 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */ dib8000_update_pll()
801 dib8000_write_word(state, 898, 0x0004); /* sad */ dib8000_update_pll()
811 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */ dib8000_update_pll()
821 dib8000_write_word(st, 1029, st->cfg.gpio_dir); dib8000_reset_gpio()
822 dib8000_write_word(st, 1030, st->cfg.gpio_val); dib8000_reset_gpio()
826 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos); dib8000_reset_gpio()
828 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div); dib8000_reset_gpio()
837 dib8000_write_word(st, 1029, st->cfg.gpio_dir); dib8000_cfg_gpio()
842 dib8000_write_word(st, 1030, st->cfg.gpio_val); dib8000_cfg_gpio()
1037 dib8000_write_word(state, 1287, 0x0003); dib8000_reset()
1050 dib8000_write_word(state, 770, 0xffff); dib8000_reset()
1051 dib8000_write_word(state, 771, 0xffff); dib8000_reset()
1052 dib8000_write_word(state, 772, 0xfffc); dib8000_reset()
1053 dib8000_write_word(state, 898, 0x000c); /* restart sad */ dib8000_reset()
1055 dib8000_write_word(state, 1280, 0x0045); dib8000_reset()
1057 dib8000_write_word(state, 1280, 0x004d); dib8000_reset()
1058 dib8000_write_word(state, 1281, 0x000c); dib8000_reset()
1060 dib8000_write_word(state, 770, 0x0000); dib8000_reset()
1061 dib8000_write_word(state, 771, 0x0000); dib8000_reset()
1062 dib8000_write_word(state, 772, 0x0000); dib8000_reset()
1063 dib8000_write_word(state, 898, 0x0004); // sad dib8000_reset()
1064 dib8000_write_word(state, 1280, 0x0000); dib8000_reset()
1065 dib8000_write_word(state, 1281, 0x0000); dib8000_reset()
1070 dib8000_write_word(state, 906, state->cfg.drives); dib8000_reset()
1074 dib8000_write_word(state, 906, 0x2d98); dib8000_reset()
1080 dib8000_write_word(state, 898, 0x0004); dib8000_reset()
1094 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ dib8000_reset()
1096 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ dib8000_reset()
1106 dib8000_write_word(state, r, *n++); dib8000_reset()
1117 dib8000_write_word(state, 903, state->cfg.div_cfg); dib8000_reset()
1120 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); dib8000_reset()
1130 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); dib8000_reset()
1142 dib8000_write_word(state, 770, 0x0a00); dib8000_restart_agc()
1143 dib8000_write_word(state, 770, 0x0000); dib8000_restart_agc()
1186 dib8000_write_word(state, 76, agc->setup); dib8000_set_agc_config()
1187 dib8000_write_word(state, 77, agc->inv_gain); dib8000_set_agc_config()
1188 dib8000_write_word(state, 78, agc->time_stabiliz); dib8000_set_agc_config()
1189 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); dib8000_set_agc_config()
1192 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); dib8000_set_agc_config()
1193 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); dib8000_set_agc_config()
1200 dib8000_write_word(state, 106, state->wbd_ref); dib8000_set_agc_config()
1202 dib8000_write_word(state, 106, agc->wbd_ref); dib8000_set_agc_config()
1206 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); dib8000_set_agc_config()
1209 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); dib8000_set_agc_config()
1210 dib8000_write_word(state, 108, agc->agc1_max); dib8000_set_agc_config()
1211 dib8000_write_word(state, 109, agc->agc1_min); dib8000_set_agc_config()
1212 dib8000_write_word(state, 110, agc->agc2_max); dib8000_set_agc_config()
1213 dib8000_write_word(state, 111, agc->agc2_min); dib8000_set_agc_config()
1214 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); dib8000_set_agc_config()
1215 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); dib8000_set_agc_config()
1216 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); dib8000_set_agc_config()
1217 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); dib8000_set_agc_config()
1219 dib8000_write_word(state, 75, agc->agc1_pt3); dib8000_set_agc_config()
1221 dib8000_write_word(state, 923, dib8000_set_agc_config()
1257 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); dib8000_agc_soft_split()
1279 dib8000_write_word(state, 1946, dib8000_agc_startup()
1282 dib8000_write_word(state, 1947, reg | (1<<14) | dib8000_agc_startup()
1287 dib8000_write_word(state, 1920, (reg | 0x3) & dib8000_agc_startup()
1350 dib8000_write_word(state, 1798, reg); dib8096p_host_bus_drive()
1355 dib8000_write_word(state, 1799, reg); dib8096p_host_bus_drive()
1361 dib8000_write_word(state, 1800, reg); dib8096p_host_bus_drive()
1366 dib8000_write_word(state, 1801, reg); dib8096p_host_bus_drive()
1372 dib8000_write_word(state, 1802, reg); dib8096p_host_bus_drive()
1400 dib8000_write_word(state, 1615, 1); dib8096p_cfg_DibTx()
1401 dib8000_write_word(state, 1603, P_Kin); dib8096p_cfg_DibTx()
1402 dib8000_write_word(state, 1605, P_Kout); dib8096p_cfg_DibTx()
1403 dib8000_write_word(state, 1606, insertExtSynchro); dib8096p_cfg_DibTx()
1404 dib8000_write_word(state, 1608, synchroMode); dib8096p_cfg_DibTx()
1405 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); dib8096p_cfg_DibTx()
1406 dib8000_write_word(state, 1610, syncWord & 0xffff); dib8096p_cfg_DibTx()
1407 dib8000_write_word(state, 1612, syncSize); dib8096p_cfg_DibTx()
1408 dib8000_write_word(state, 1615, 0); dib8096p_cfg_DibTx()
1422 dib8000_write_word(state, 1542, syncFreq); dib8096p_cfg_DibRx()
1425 dib8000_write_word(state, 1554, 1); dib8096p_cfg_DibRx()
1426 dib8000_write_word(state, 1536, P_Kin); dib8096p_cfg_DibRx()
1427 dib8000_write_word(state, 1537, P_Kout); dib8096p_cfg_DibRx()
1428 dib8000_write_word(state, 1539, synchroMode); dib8096p_cfg_DibRx()
1429 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); dib8096p_cfg_DibRx()
1430 dib8000_write_word(state, 1541, syncWord & 0xffff); dib8096p_cfg_DibRx()
1431 dib8000_write_word(state, 1543, syncSize); dib8096p_cfg_DibRx()
1432 dib8000_write_word(state, 1544, dataOutRate); dib8096p_cfg_DibRx()
1433 dib8000_write_word(state, 1554, 0); dib8096p_cfg_DibRx()
1451 dib8000_write_word(state, 1287, reg_1287); dib8096p_enMpegMux()
1469 dib8000_write_word(state, 1287, reg_1287); dib8096p_configMpegMux()
1494 dib8000_write_word(state, 1288, reg_1288); dib8096p_setDibTxMux()
1519 dib8000_write_word(state, 1288, reg_1288); dib8096p_setHostBusMux()
1541 dib8000_write_word(state, 1287, reg_1287); dib8096p_set_diversity_in()
1640 ret |= dib8000_write_word(state, 299, smo_mode); dib8096p_set_output_mode()
1642 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold); dib8096p_set_output_mode()
1643 ret |= dib8000_write_word(state, 1286, outreg); dib8096p_set_output_mode()
1683 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); dib8096p_tuner_write_serpar()
1684 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); dib8096p_tuner_write_serpar()
1704 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); dib8096p_tuner_read_serpar()
1740 dib8000_write_word(state, apb_address, dib8096p_rw_on_apb()
1858 dib8000_write_word(state, 921, word); dib8096p_tuner_xfer()
1907 dib8000_write_word(state, 1922, en_cur_state); dib8096p_tuner_sleep()
1959 dib8000_write_word(state, 29, (u16) (timf >> 16)); dib8000_update_timf()
1960 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); dib8000_update_timf()
2033 dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv); dib8000_set_layer()
2076 dib8000_write_word(state, 215 + i, adp[i]); dib8000_adp_fine_tune()
2085 dib8000_write_word(state, 116, ana_gain); dib8000_update_ana_gain()
2090 dib8000_write_word(state, 80 + i, adc_target_16dB[i]); dib8000_update_ana_gain()
2093 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); dib8000_update_ana_gain()
2103 dib8000_write_word(state, 117 + mode, ana_fe[mode]); dib8000_load_ana_fe_coefs()
2143 dib8000_write_word(state, 180, (16 << 6) | 9); dib8000_set_13seg_channel()
2144 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); dib8000_set_13seg_channel()
2147 dib8000_write_word(state, 181+i, coff_pow); dib8000_set_13seg_channel()
2151 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); dib8000_set_13seg_channel()
2154 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); dib8000_set_13seg_channel()
2156 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); dib8000_set_13seg_channel()
2158 dib8000_write_word(state, 228, 0); /* default value */ dib8000_set_13seg_channel()
2159 dib8000_write_word(state, 265, 31); /* default value */ dib8000_set_13seg_channel()
2160 dib8000_write_word(state, 205, 0x200f); /* init value */ dib8000_set_13seg_channel()
2169 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */ dib8000_set_13seg_channel()
2179 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */ dib8000_set_subchannel_prbs()
2188 dib8000_write_word(state, 352, state->seg_diff_mask); dib8000_small_fine_tune()
2189 dib8000_write_word(state, 353, state->seg_mask); dib8000_small_fine_tune()
2192 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5); dib8000_small_fine_tune()
2262 dib8000_write_word(state, 343 + i, ncoeff[i]); dib8000_small_fine_tune()
2275 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ dib8000_set_sb_channel()
2276 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */ dib8000_set_sb_channel()
2278 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ dib8000_set_sb_channel()
2279 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */ dib8000_set_sb_channel()
2287 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); dib8000_set_sb_channel()
2291 dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3); dib8000_set_sb_channel()
2293 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */ dib8000_set_sb_channel()
2294 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */ dib8000_set_sb_channel()
2300 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); dib8000_set_sb_channel()
2302 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); dib8000_set_sb_channel()
2305 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); dib8000_set_sb_channel()
2308 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); dib8000_set_sb_channel()
2310 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); dib8000_set_sb_channel()
2314 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */ dib8000_set_sb_channel()
2315 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ dib8000_set_sb_channel()
2318 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */ dib8000_set_sb_channel()
2322 dib8000_write_word(state, 181+i, coff[i]); dib8000_set_sb_channel()
2323 dib8000_write_word(state, 184+i, coff[i]); dib8000_set_sb_channel()
2331 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */ dib8000_set_sb_channel()
2334 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */ dib8000_set_sb_channel()
2336 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ dib8000_set_sb_channel()
2351 dib8000_write_word(state, 10, (seq << 4)); dib8000_set_isdbt_common_channel()
2358 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); dib8000_set_isdbt_common_channel()
2360 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4)); dib8000_set_isdbt_common_channel()
2377 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); dib8000_set_isdbt_common_channel()
2379 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */ dib8000_set_isdbt_common_channel()
2389 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); dib8000_set_isdbt_common_channel()
2429 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */ dib8000_set_isdbt_common_channel()
2430 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */ dib8000_set_isdbt_common_channel()
2433 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */ dib8000_set_isdbt_common_channel()
2434 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */ dib8000_set_isdbt_common_channel()
2435 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */ dib8000_set_isdbt_common_channel()
2438 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */ dib8000_set_isdbt_common_channel()
2440 dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */ dib8000_set_isdbt_common_channel()
2442 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */ dib8000_set_isdbt_common_channel()
2443 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ dib8000_set_isdbt_common_channel()
2445 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ dib8000_set_isdbt_common_channel()
2454 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */ dib8000_set_isdbt_common_channel()
2455 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */ dib8000_set_isdbt_common_channel()
2456 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */ dib8000_set_isdbt_common_channel()
2457 /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */ dib8000_set_isdbt_common_channel()
2461 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */ dib8000_set_isdbt_common_channel()
2482 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); dib8000_wait_lock()
2483 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); dib8000_wait_lock()
2500 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */ dib8000_autosearch_start()
2501 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */ dib8000_autosearch_start()
2503 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */ dib8000_autosearch_start()
2504 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ dib8000_autosearch_start()
2505 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */ dib8000_autosearch_start()
2506 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */ dib8000_autosearch_start()
2507 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */ dib8000_autosearch_start()
2508 dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */ dib8000_autosearch_start()
2515 dib8000_write_word(state, 17, 0); dib8000_autosearch_start()
2516 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */ dib8000_autosearch_start()
2517 dib8000_write_word(state, 19, 0); dib8000_autosearch_start()
2518 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */ dib8000_autosearch_start()
2519 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */ dib8000_autosearch_start()
2520 dib8000_write_word(state, 22, value & 0xffff); dib8000_autosearch_start()
2523 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */ dib8000_autosearch_start()
2525 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */ dib8000_autosearch_start()
2526 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */ dib8000_autosearch_start()
2529 dib8000_write_word(state, 356, 0); dib8000_autosearch_start()
2530 dib8000_write_word(state, 357, 0x111); dib8000_autosearch_start()
2532 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */ dib8000_autosearch_start()
2533 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */ dib8000_autosearch_start()
2534 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */ dib8000_autosearch_start()
2551 dib8000_write_word(state, 6, 0x4); dib8000_autosearch_start()
2553 dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */ dib8000_autosearch_start()
2555 dib8000_write_word(state, 7, 0x8); dib8000_autosearch_start()
2556 dib8000_write_word(state, 8, 0x1000); dib8000_autosearch_start()
2564 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */ dib8000_autosearch_start()
2567 dib8000_write_word(state, 356, 0); dib8000_autosearch_start()
2568 dib8000_write_word(state, 357, 0xf); dib8000_autosearch_start()
2571 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); dib8000_autosearch_start()
2573 dib8000_write_word(state, 0, (u16)value); dib8000_autosearch_start()
2586 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); dib8000_autosearch_start()
2593 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */ dib8000_autosearch_start()
2602 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ dib8000_autosearch_start()
2612 dib8000_write_word(state, 6, 0x4); dib8000_autosearch_start()
2614 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10)); dib8000_autosearch_start()
2616 dib8000_write_word(state, 7, 0x8); dib8000_autosearch_start()
2617 dib8000_write_word(state, 8, 0x1000); dib8000_autosearch_start()
2626 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); dib8000_autosearch_start()
2628 dib8000_write_word(state, 0, (u16)value); dib8000_autosearch_start()
2665 dib8000_write_word(state, 771, tmp & 0xfffd); dib8000_viterbi_state()
2667 dib8000_write_word(state, 771, tmp | (1<<1)); dib8000_viterbi_state()
2706 dib8000_write_word(state, 26, invert); dib8000_set_dds()
2707 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff); dib8000_set_dds()
2708 dib8000_write_word(state, 28, (u16)(dds & 0xffff)); dib8000_set_dds()
2730 dib8000_write_word(state, 26, c->inversion ^ i); dib8000_set_frequency_offset()
2734 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); dib8000_set_frequency_offset()
2806 dib8000_write_word(state, 32, reg_32); dib8000_set_isdbt_loop_params()
2807 dib8000_write_word(state, 37, reg_37); dib8000_set_isdbt_loop_params()
2812 dib8000_write_word(state, 770, 0x4000); dib8000_demod_restart()
2813 dib8000_write_word(state, 770, 0x0000); dib8000_demod_restart()
2841 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); dib8000_set_sync_wait()
2896 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ dib8090p_init_sdram()
2898 dib8000_write_word(state, 1803, (7 << 2)); dib8090p_init_sdram()
2901 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */ dib8090p_init_sdram()
2902 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */ dib8090p_init_sdram()
3031 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); dib8000_tune()
3045 dib8000_write_word(state, 108, agc1); dib8000_tune()
3046 dib8000_write_word(state, 109, agc1); dib8000_tune()
3047 dib8000_write_word(state, 110, agc2); dib8000_tune()
3048 dib8000_write_word(state, 111, agc2); dib8000_tune()
3319 dib8000_write_word(state, 108, state->agc1_max); dib8000_tune()
3320 dib8000_write_word(state, 109, state->agc1_min); dib8000_tune()
3321 dib8000_write_word(state, 110, state->agc2_max); dib8000_tune()
3322 dib8000_write_word(state, 111, state->agc2_min); dib8000_tune()
4388 return dib8000_write_word(st, 299, val); dib8000_pid_filter_ctrl()
4395 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0); dib8000_pid_filter()
4480 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */ dib8000_init()
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