| H A D | dib0090.c | 248 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) dib0090_write_reg() function
339 dib0090_write_reg(state, r++, *b++); dib0090_write_regs()
531 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); dib0090_reset_digital()
535 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ dib0090_reset_digital()
537 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0); dib0090_reset_digital()
539 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8) dib0090_reset_digital()
542 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8) dib0090_reset_digital()
554 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
558 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
562 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
566 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
583 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
588 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
672 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_wakeup()
688 dib0090_write_reg(state, 0x04, 0); dib0090_dcc_freq()
690 dib0090_write_reg(state, 0x04, 1); dib0090_dcc_freq()
1025 dib0090_write_reg(state, gain_reg_addr[i], v); dib0090_gain_apply()
1045 dib0090_write_reg(state, 0x2a, 0xffff); dib0090_set_rframp_pwm()
1065 dib0090_write_reg(state, 0x33, 0xffff); dib0090_set_bbramp_pwm()
1126 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11)); dib0090_pwm_gain_reset()
1130 dib0090_write_reg(state, 0x04, 3); dib0090_pwm_gain_reset()
1132 dib0090_write_reg(state, 0x04, 1); dib0090_pwm_gain_reset()
1133 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */ dib0090_pwm_gain_reset()
1142 dib0090_write_reg(state, 0x04, DC_servo_cutoff); dib0090_set_dc_servo()
1166 dib0090_write_reg(state, 0x04, 0x0); dib0090_gain_control()
1194 dib0090_write_reg(state, 0x32, 0); dib0090_gain_control()
1195 dib0090_write_reg(state, 0x39, 0); dib0090_gain_control()
1284 dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */ dib0090_gain_control()
1285 dib0090_write_reg(state, 0x04, 0x0); dib0090_gain_control()
1289 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); dib0090_gain_control()
1290 dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */ dib0090_gain_control()
1356 dib0090_write_reg(state, 0x10, state->wbdmux); dib0090_get_wbd_target()
1382 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) dib0090_set_switch()
1393 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) dib0090_set_vga()
1491 dib0090_write_reg(state, r, pgm_read_word(n++)); dib0090_set_default_config()
1517 dib0090_write_reg(state, 0x22, 0x10); dib0090_set_EFUSE()
1543 dib0090_write_reg(state, 0x13, (h << 10)); dib0090_set_EFUSE()
1545 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */ dib0090_set_EFUSE()
1564 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); dib0090_reset()
1566 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); dib0090_reset()
1572 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ dib0090_reset()
1583 dib0090_write_reg(state, 0x14, dib0090_reset()
1586 dib0090_write_reg(state, 0x14, 1); dib0090_reset()
1588 dib0090_write_reg(state, 0x14, 2); dib0090_reset()
1605 dib0090_write_reg(state, 0x1f, 0x7); dib0090_get_offset()
1613 dib0090_write_reg(state, 0x1f, 0x4); dib0090_get_offset()
1671 dib0090_write_reg(state, state->dc->addr, *val); dib0090_set_trim()
1689 dib0090_write_reg(state, 0x24, reg); dib0090_dc_offset_calibration()
1692 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); dib0090_dc_offset_calibration()
1693 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); dib0090_dc_offset_calibration()
1705 dib0090_write_reg(state, 0x01, state->dc->bb1); dib0090_dc_offset_calibration()
1706 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); dib0090_dc_offset_calibration()
1768 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); dib0090_dc_offset_calibration()
1769 dib0090_write_reg(state, 0x1f, 0x7); dib0090_dc_offset_calibration()
1803 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); dib0090_wbd_calibration()
1805 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); dib0090_wbd_calibration()
1839 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ dib0090_set_bandwidth()
1841 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */ dib0090_set_bandwidth()
1842 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */ dib0090_set_bandwidth()
1844 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */ dib0090_set_bandwidth()
1846 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ dib0090_set_bandwidth()
1847 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */ dib0090_set_bandwidth()
2069 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) dib0090_update_tuning_table_7090()
2071 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) dib0090_update_tuning_table_7090()
2092 dib0090_write_reg(state, 0x10, 0x2B1); dib0090_captrim_search()
2093 dib0090_write_reg(state, 0x1e, 0x0032); dib0090_captrim_search()
2115 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); dib0090_captrim_search()
2120 dib0090_write_reg(state, 0x18, lo4 | state->captrim); dib0090_captrim_search()
2129 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); dib0090_captrim_search()
2170 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); dib0090_captrim_search()
2190 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); dib0090_get_temperature()
2193 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); dib0090_get_temperature()
2201 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); dib0090_get_temperature()
2215 dib0090_write_reg(state, 0x13, state->bias); dib0090_get_temperature()
2216 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ dib0090_get_temperature()
2221 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_get_temperature()
2254 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); dib0090_tune()
2258 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_tune()
2277 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); dib0090_tune()
2364 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); dib0090_tune()
2440 dib0090_write_reg(state, 0x15, (u16) FBDiv); dib0090_tune()
2442 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); dib0090_tune()
2444 dib0090_write_reg(state, 0x16, (Den << 8) | 1); dib0090_tune()
2445 dib0090_write_reg(state, 0x17, (u16) Rest); dib0090_tune()
2446 dib0090_write_reg(state, 0x19, lo5); dib0090_tune()
2447 dib0090_write_reg(state, 0x1c, lo6); dib0090_tune()
2453 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); dib0090_tune()
2470 dib0090_write_reg(state, 0x1e, 0x07ff); dib0090_tune()
2488 dib0090_write_reg(state, 0x10, state->wbdmux); dib0090_tune()
2492 dib0090_write_reg(state, 0x09, tune->lna_bias); dib0090_tune()
2493 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); dib0090_tune()
2495 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); dib0090_tune()
2497 dib0090_write_reg(state, 0x0c, tune->v2i); dib0090_tune()
2498 dib0090_write_reg(state, 0x0d, tune->mix); dib0090_tune()
2499 dib0090_write_reg(state, 0x0e, tune->load); dib0090_tune()
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