Searched refs:ddi_pll_sel (Results 1 – 6 of 6) sorted by relevance
373 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()374 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); in hsw_fdi_link_train()779 dpll = pipe_config->ddi_pll_sel; in skl_ddi_clock_get()832 val = pipe_config->ddi_pll_sel; in hsw_ddi_clock_get()983 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); in hsw_ddi_pll_select()1208 crtc_state->ddi_pll_sel = pll->id + 1; in skl_ddi_pll_select()1537 uint32_t dpll = crtc->config->ddi_pll_sel; in intel_ddi_pre_enable()1569 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); in intel_ddi_pre_enable()1570 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); in intel_ddi_pre_enable()
177 intel_crtc->config->ddi_pll_sel); in intel_mst_pre_enable_dp()
326 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; in intel_crt_compute_config()
344 uint32_t ddi_pll_sel; member
1086 pipe_config->ddi_pll_sel = SKL_DPLL0; in skl_edp_set_pll_config()1129 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; in hsw_dp_set_ddi_pll_sel()1132 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; in hsw_dp_set_ddi_pll_sel()1135 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; in hsw_dp_set_ddi_pll_sel()
8491 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); in skylake_get_ddi_pll()8493 switch (pipe_config->ddi_pll_sel) { in skylake_get_ddi_pll()8519 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); in haswell_get_ddi_pll()8521 switch (pipe_config->ddi_pll_sel) { in haswell_get_ddi_pll()11104 PIPE_CONF_CHECK_X(ddi_pll_sel); in intel_pipe_config_compare()