Searched refs:dclk_div (Results 1 – 6 of 6) sorted by relevance
| /linux-4.1.27/drivers/video/fbdev/geode/ |
| D | display_gx1.c | 84 u32 gcfg, tcfg, ocfg, dclk_div, val; in gx1_set_mode() local
112 dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */ in gx1_set_mode()
113 gcfg |= dclk_div; in gx1_set_mode()
126 gcfg = DC_GCFG_VRDY | dclk_div; in gx1_set_mode()
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| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| D | radeon_uvd.c | 930 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local
947 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
953 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
959 *optimal_dclk_div = dclk_div; in radeon_uvd_calc_upll_dividers()
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| D | rv770.c | 49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
69 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
75 dclk_div -= 1; in rv770_set_uvd_clocks()
99 UPLL_SW_HILEN2(dclk_div >> 1) | in rv770_set_uvd_clocks()
100 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), in rv770_set_uvd_clocks()
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| D | r600.c | 152 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
181 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
210 UPLL_SW_HILEN2(dclk_div >> 1) | in r600_set_uvd_clocks()
211 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | in r600_set_uvd_clocks()
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| D | evergreen.c | 1118 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1137 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1176 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
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| D | si.c | 7275 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7293 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7334 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
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