Searched refs:counter (Results 1 - 200 of 2220) sorted by relevance

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/linux-4.1.27/include/linux/
H A Dpage_counter.h24 static inline void page_counter_init(struct page_counter *counter, page_counter_init() argument
27 atomic_long_set(&counter->count, 0); page_counter_init()
28 counter->limit = PAGE_COUNTER_MAX; page_counter_init()
29 counter->parent = parent; page_counter_init()
32 static inline unsigned long page_counter_read(struct page_counter *counter) page_counter_read() argument
34 return atomic_long_read(&counter->count); page_counter_read()
37 void page_counter_cancel(struct page_counter *counter, unsigned long nr_pages);
38 void page_counter_charge(struct page_counter *counter, unsigned long nr_pages);
39 int page_counter_try_charge(struct page_counter *counter,
42 void page_counter_uncharge(struct page_counter *counter, unsigned long nr_pages);
43 int page_counter_limit(struct page_counter *counter, unsigned long limit);
47 static inline void page_counter_reset_watermark(struct page_counter *counter) page_counter_reset_watermark() argument
49 counter->watermark = page_counter_read(counter); page_counter_reset_watermark()
H A Dtimecounter.h26 * struct cyclecounter - hardware abstraction for a free running counter
28 * Depending on which hardware it reads, the cycle counter may wrap
49 * cycle counter wrap around. Initialize with
53 * cycle counter hardware, locking issues and reading the time
54 * more often than the cycle counter wraps around. The nanosecond
55 * counter will only wrap around after ~585 years.
57 * @cc: the cycle counter used by this instance
58 * @cycle_last: most recent cycle counter value seen by
73 * cyclecounter_cyc2ns - converts cycle counter cycles to nanoseconds
74 * @cc: Pointer to cycle counter.
99 * timecounter_init - initialize a time counter
100 * @tc: Pointer to time counter which is to be initialized/reset
101 * @cc: A cycle counter, ready to be used.
106 * the time stamp counter by the number of elapsed nanoseconds.
115 * @tc: Pointer to time counter.
123 * timecounter_cyc2time - convert a cycle counter to same
126 * @tc: Pointer to time counter.
133 * This allows conversion of cycle counter values which were generated
H A Dcnt32_to_63.h2 * Extend a 32-bit counter to 63 bits
34 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * @cnt_lo: The low part of the counter
42 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
48 * counter wraps around.
59 * 32-bit counter;
62 * 32-bit counter half period minus the longest period between two
73 * meaning that it should be a direct reference to the counter data which
H A Dproportions.h25 * The total event counter aka 'time'.
28 * counter bits, the remaining upper bits the period counter.
53 * the local events counter
83 * cycle counter and fraction multiply.
104 * the local events counter
H A Dsched_clock.h2 * sched_clock.h: support for extending counters to full 64-bit ns counter
H A Dpercpu_counter.h4 * A simple "approximate counter" for use in ext2 and ext3 superblocks.
6 * WARNING: these things are HUGE. 4 kbytes per counter on 32-way P4.
74 * number for some counter which should never be negative.
/linux-4.1.27/lib/
H A Datomic64_test.c30 BUG_ON(v.counter != r); test_atomic64()
34 BUG_ON(v.counter != r); test_atomic64()
40 BUG_ON(v.counter != r); test_atomic64()
45 BUG_ON(v.counter != r); test_atomic64()
50 BUG_ON(v.counter != r); test_atomic64()
55 BUG_ON(v.counter != r); test_atomic64()
60 BUG_ON(v.counter != r); test_atomic64()
65 BUG_ON(v.counter != r); test_atomic64()
70 BUG_ON(v.counter != r); test_atomic64()
75 BUG_ON(v.counter != r); test_atomic64()
80 BUG_ON(v.counter != r); test_atomic64()
85 BUG_ON(v.counter != r); test_atomic64()
90 BUG_ON(v.counter != r); test_atomic64()
95 BUG_ON(v.counter != r); test_atomic64()
100 BUG_ON(v.counter != r); test_atomic64()
105 BUG_ON(v.counter != r); test_atomic64()
109 BUG_ON(v.counter != r); test_atomic64()
113 BUG_ON(v.counter != r); test_atomic64()
118 BUG_ON(v.counter != r); test_atomic64()
124 BUG_ON(v.counter != r); test_atomic64()
128 BUG_ON(v.counter != r); test_atomic64()
132 BUG_ON(v.counter != r); test_atomic64()
140 BUG_ON(v.counter != r); test_atomic64()
144 BUG_ON(v.counter != r); test_atomic64()
149 BUG_ON(v.counter != r); test_atomic64()
H A Datomic64.c56 val = v->counter; atomic64_read()
68 v->counter = i; atomic64_set()
80 v->counter c_op a; \
93 val = (v->counter c_op a); \
117 val = v->counter - 1; atomic64_dec_if_positive()
119 v->counter = val; atomic64_dec_if_positive()
132 val = v->counter; atomic64_cmpxchg()
134 v->counter = n; atomic64_cmpxchg()
147 val = v->counter; atomic64_xchg()
148 v->counter = new; atomic64_xchg()
161 if (v->counter != u) { atomic64_add_unless()
162 v->counter += a; atomic64_add_unless()
H A Ddec_and_lock.c22 /* Subtract 1 from counter unless that drops it to 0 (ie. it was 1) */ _atomic_dec_and_lock()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dni_tiocmd.c50 static void ni_tio_configure_dma(struct ni_gpct *counter, ni_tio_configure_dma() argument
53 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_configure_dma()
54 unsigned cidx = counter->counter_index; ni_tio_configure_dma()
67 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits); ni_tio_configure_dma()
81 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits); ni_tio_configure_dma()
90 struct ni_gpct *counter = s->private; ni_tio_input_inttrig() local
98 spin_lock_irqsave(&counter->lock, flags); ni_tio_input_inttrig()
99 if (counter->mite_chan) ni_tio_input_inttrig()
100 mite_dma_arm(counter->mite_chan); ni_tio_input_inttrig()
103 spin_unlock_irqrestore(&counter->lock, flags); ni_tio_input_inttrig()
106 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); ni_tio_input_inttrig()
114 struct ni_gpct *counter = s->private; ni_tio_input_cmd() local
115 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_input_cmd()
116 unsigned cidx = counter->counter_index; ni_tio_input_cmd()
123 counter->mite_chan->dir = COMEDI_INPUT; ni_tio_input_cmd()
127 mite_prep_dma(counter->mite_chan, 32, 32); ni_tio_input_cmd()
130 mite_prep_dma(counter->mite_chan, 16, 32); ni_tio_input_cmd()
136 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0); ni_tio_input_cmd()
137 ni_tio_configure_dma(counter, true, true); ni_tio_input_cmd()
143 mite_dma_arm(counter->mite_chan); ni_tio_input_cmd()
146 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); ni_tio_input_cmd()
148 ret = ni_tio_arm(counter, 1, cmd->start_arg); ni_tio_input_cmd()
155 struct ni_gpct *counter = s->private; ni_tio_output_cmd() local
157 dev_err(counter->counter_dev->dev->class_dev, ni_tio_output_cmd()
161 counter->mite_chan->dir = COMEDI_OUTPUT; ni_tio_output_cmd()
162 mite_prep_dma(counter->mite_chan, 32, 32); ni_tio_output_cmd()
163 ni_tio_configure_dma(counter, true, false); ni_tio_output_cmd()
164 mite_dma_arm(counter->mite_chan); ni_tio_output_cmd()
165 return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); ni_tio_output_cmd()
171 struct ni_gpct *counter = s->private; ni_tio_cmd_setup() local
172 unsigned cidx = counter->counter_index; ni_tio_cmd_setup()
185 retval = ni_tio_set_gate_src(counter, 0, gate_source); ni_tio_cmd_setup()
187 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ni_tio_cmd_setup()
196 struct ni_gpct *counter = s->private; ni_tio_cmd() local
202 spin_lock_irqsave(&counter->lock, flags); ni_tio_cmd()
203 if (!counter->mite_chan) { ni_tio_cmd()
204 dev_err(counter->counter_dev->dev->class_dev, ni_tio_cmd()
206 dev_err(counter->counter_dev->dev->class_dev, ni_tio_cmd()
218 spin_unlock_irqrestore(&counter->lock, flags); ni_tio_cmd()
227 struct ni_gpct *counter = s->private; ni_tio_cmdtest() local
234 if (ni_tio_counting_mode_registers_present(counter->counter_dev)) ni_tio_cmdtest()
296 int ni_tio_cancel(struct ni_gpct *counter) ni_tio_cancel() argument
298 unsigned cidx = counter->counter_index; ni_tio_cancel()
301 ni_tio_arm(counter, 0, 0); ni_tio_cancel()
302 spin_lock_irqsave(&counter->lock, flags); ni_tio_cancel()
303 if (counter->mite_chan) ni_tio_cancel()
304 mite_dma_disarm(counter->mite_chan); ni_tio_cancel()
305 spin_unlock_irqrestore(&counter->lock, flags); ni_tio_cancel()
306 ni_tio_configure_dma(counter, false, false); ni_tio_cancel()
308 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ni_tio_cancel()
314 /* During buffered input counter operation for e-series, the gate
317 static int should_ack_gate(struct ni_gpct *counter) should_ack_gate() argument
322 switch (counter->counter_dev->variant) { should_ack_gate()
330 spin_lock_irqsave(&counter->lock, flags); should_ack_gate()
332 if (!counter->mite_chan || should_ack_gate()
333 counter->mite_chan->dir != COMEDI_INPUT || should_ack_gate()
334 (mite_done(counter->mite_chan))) { should_ack_gate()
338 spin_unlock_irqrestore(&counter->lock, flags); should_ack_gate()
344 static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, ni_tio_acknowledge_and_confirm() argument
350 unsigned cidx = counter->counter_index; ni_tio_acknowledge_and_confirm()
351 const unsigned short gxx_status = read_register(counter, ni_tio_acknowledge_and_confirm()
353 const unsigned short gi_status = read_register(counter, ni_tio_acknowledge_and_confirm()
372 if (counter->counter_dev->variant != ni_tio_acknowledge_and_confirm()
385 if (should_ack_gate(counter)) ni_tio_acknowledge_and_confirm()
389 write_register(counter, ack, NITIO_INT_ACK_REG(cidx)); ni_tio_acknowledge_and_confirm()
390 if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) & ni_tio_acknowledge_and_confirm()
396 if (read_register(counter, NITIO_STATUS2_REG(cidx)) & ni_tio_acknowledge_and_confirm()
398 dev_info(counter->counter_dev->dev->class_dev, ni_tio_acknowledge_and_confirm()
407 void ni_tio_acknowledge(struct ni_gpct *counter) ni_tio_acknowledge() argument
409 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); ni_tio_acknowledge()
413 void ni_tio_handle_interrupt(struct ni_gpct *counter, ni_tio_handle_interrupt() argument
416 unsigned cidx = counter->counter_index; ni_tio_handle_interrupt()
423 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error, ni_tio_handle_interrupt()
426 dev_notice(counter->counter_dev->dev->class_dev, ni_tio_handle_interrupt()
432 switch (counter->counter_dev->variant) { ni_tio_handle_interrupt()
435 if (read_register(counter, NITIO_DMA_STATUS_REG(cidx)) & ni_tio_handle_interrupt()
437 dev_notice(counter->counter_dev->dev->class_dev, ni_tio_handle_interrupt()
445 spin_lock_irqsave(&counter->lock, flags); ni_tio_handle_interrupt()
446 if (!counter->mite_chan) { ni_tio_handle_interrupt()
447 spin_unlock_irqrestore(&counter->lock, flags); ni_tio_handle_interrupt()
450 gpct_mite_status = mite_get_status(counter->mite_chan); ni_tio_handle_interrupt()
453 counter->mite_chan->mite->mite_io_addr + ni_tio_handle_interrupt()
454 MITE_CHOR(counter->mite_chan->channel)); ni_tio_handle_interrupt()
455 mite_sync_input_dma(counter->mite_chan, s); ni_tio_handle_interrupt()
456 spin_unlock_irqrestore(&counter->lock, flags); ni_tio_handle_interrupt()
460 void ni_tio_set_mite_channel(struct ni_gpct *counter, ni_tio_set_mite_channel() argument
465 spin_lock_irqsave(&counter->lock, flags); ni_tio_set_mite_channel()
466 counter->mite_chan = mite_chan; ni_tio_set_mite_channel()
467 spin_unlock_irqrestore(&counter->lock, flags); ni_tio_set_mite_channel()
H A Dni_tio.c32 * originally based on the counter code from ni_660x.c and
182 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter) ni_tio_reset_count_and_disarm() argument
184 unsigned cidx = counter->counter_index; ni_tio_reset_count_and_disarm()
186 write_register(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx)); ni_tio_reset_count_and_disarm()
189 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter, ni_tio_clock_period_ps() argument
212 return counter->clock_period_ps; ni_tio_clock_period_ps()
231 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter) ni_tio_clock_src_modifiers() argument
233 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_clock_src_modifiers()
234 unsigned cidx = counter->counter_index; ni_tio_clock_src_modifiers()
236 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx)); ni_tio_clock_src_modifiers()
239 if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) & ni_tio_clock_src_modifiers()
249 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter) ni_m_series_clock_src_select() argument
251 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_m_series_clock_src_select()
252 unsigned cidx = counter->counter_index; ni_m_series_clock_src_select()
258 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter, ni_m_series_clock_src_select()
310 clock_source |= ni_tio_clock_src_modifiers(counter); ni_m_series_clock_src_select()
314 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter) ni_660x_clock_src_select() argument
317 unsigned cidx = counter->counter_index; ni_660x_clock_src_select()
321 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter, ni_660x_clock_src_select()
367 clock_source |= ni_tio_clock_src_modifiers(counter); ni_660x_clock_src_select()
371 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter) ni_tio_generic_clock_src_select() argument
373 switch (counter->counter_dev->variant) { ni_tio_generic_clock_src_select()
377 return ni_m_series_clock_src_select(counter); ni_tio_generic_clock_src_select()
379 return ni_660x_clock_src_select(counter); ni_tio_generic_clock_src_select()
383 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync) ni_tio_set_sync_mode() argument
385 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_sync_mode()
386 unsigned cidx = counter->counter_index; ni_tio_set_sync_mode()
395 mode = ni_tio_get_soft_copy(counter, counting_mode_reg); ni_tio_set_sync_mode()
407 clock_period_ps = ni_tio_clock_period_ps(counter, ni_tio_set_sync_mode()
408 ni_tio_generic_clock_src_select(counter)); ni_tio_set_sync_mode()
417 ni_tio_set_bits(counter, counting_mode_reg, ni_tio_set_sync_mode()
421 ni_tio_set_bits(counter, counting_mode_reg, ni_tio_set_sync_mode()
427 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) ni_tio_set_counter_mode() argument
429 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_counter_mode()
430 unsigned cidx = counter->counter_index; ni_tio_set_counter_mode()
457 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ni_tio_set_counter_mode()
467 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ni_tio_set_counter_mode()
470 ni_tio_set_sync_mode(counter, 0); ni_tio_set_counter_mode()
473 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK, ni_tio_set_counter_mode()
480 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ni_tio_set_counter_mode()
487 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger) ni_tio_arm() argument
489 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_arm()
490 unsigned cidx = counter->counter_index; ni_tio_arm()
529 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ni_tio_arm()
535 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx), ni_tio_arm()
653 static void ni_tio_set_source_subselect(struct ni_gpct *counter, ni_tio_set_source_subselect() argument
656 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_source_subselect()
657 unsigned cidx = counter->counter_index; ni_tio_set_source_subselect()
677 write_register(counter, counter_dev->regs[second_gate_reg], ni_tio_set_source_subselect()
681 static int ni_tio_set_clock_src(struct ni_gpct *counter, ni_tio_set_clock_src() argument
685 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_clock_src()
686 unsigned cidx = counter->counter_index; ni_tio_set_clock_src()
702 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ni_tio_set_clock_src()
704 ni_tio_set_source_subselect(counter, clock_source); ni_tio_set_clock_src()
720 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ni_tio_set_clock_src()
724 counter->clock_period_ps = period_ns * 1000; ni_tio_set_clock_src()
725 ni_tio_set_sync_mode(counter, 0); ni_tio_set_clock_src()
729 static void ni_tio_get_clock_src(struct ni_gpct *counter, ni_tio_get_clock_src() argument
735 *clock_source = ni_tio_generic_clock_src_select(counter); ni_tio_get_clock_src()
736 temp64 = ni_tio_clock_period_ps(counter, *clock_source); ni_tio_get_clock_src()
741 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source) ni_660x_set_gate() argument
744 unsigned cidx = counter->counter_index; ni_660x_set_gate()
777 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ni_660x_set_gate()
782 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source) ni_m_set_gate() argument
785 unsigned cidx = counter->counter_index; ni_m_set_gate()
819 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ni_m_set_gate()
824 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source) ni_660x_set_gate2() argument
826 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_660x_set_gate2()
827 unsigned cidx = counter->counter_index; ni_660x_set_gate2()
866 write_register(counter, counter_dev->regs[gate2_reg], gate2_reg); ni_660x_set_gate2()
870 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source) ni_m_set_gate2() argument
872 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_m_set_gate2()
873 unsigned cidx = counter->counter_index; ni_m_set_gate2()
890 write_register(counter, counter_dev->regs[gate2_reg], gate2_reg); ni_m_set_gate2()
894 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, ni_tio_set_gate_src() argument
897 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_gate_src()
898 unsigned cidx = counter->counter_index; ni_tio_set_gate_src()
906 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ni_tio_set_gate_src()
917 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ni_tio_set_gate_src()
924 return ni_m_set_gate(counter, gate_source); ni_tio_set_gate_src()
926 return ni_660x_set_gate(counter, gate_source); ni_tio_set_gate_src()
935 write_register(counter, counter_dev->regs[gate2_reg], ni_tio_set_gate_src()
945 return ni_m_set_gate2(counter, gate_source); ni_tio_set_gate_src()
947 return ni_660x_set_gate2(counter, gate_source); ni_tio_set_gate_src()
960 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index, ni_tio_set_other_src() argument
963 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_other_src()
964 unsigned cidx = counter->counter_index; ni_tio_set_other_src()
990 write_register(counter, counter_dev->regs[abz_reg], abz_reg); ni_tio_set_other_src()
1105 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index, ni_tio_get_gate_src() argument
1108 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_get_gate_src()
1109 unsigned cidx = counter->counter_index; ni_tio_get_gate_src()
1110 unsigned mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)); ni_tio_get_gate_src()
1121 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, ni_tio_get_gate_src()
1175 struct ni_gpct *counter = s->private; ni_tio_insn_config() local
1176 unsigned cidx = counter->counter_index; ni_tio_insn_config()
1181 return ni_tio_set_counter_mode(counter, data[1]); ni_tio_insn_config()
1183 return ni_tio_arm(counter, 1, data[1]); ni_tio_insn_config()
1185 ni_tio_arm(counter, 0, 0); ni_tio_insn_config()
1189 status = read_register(counter, NITIO_SHARED_STATUS_REG(cidx)); ni_tio_insn_config()
1198 return ni_tio_set_clock_src(counter, data[1], data[2]); ni_tio_insn_config()
1200 ni_tio_get_clock_src(counter, &data[1], &data[2]); ni_tio_insn_config()
1203 return ni_tio_set_gate_src(counter, data[1], data[2]); ni_tio_insn_config()
1205 return ni_tio_get_gate_src(counter, data[1], &data[2]); ni_tio_insn_config()
1207 return ni_tio_set_other_src(counter, data[1], data[2]); ni_tio_insn_config()
1209 ni_tio_reset_count_and_disarm(counter); ni_tio_insn_config()
1221 struct ni_gpct *counter = s->private; ni_tio_read_sw_save_reg() local
1222 unsigned cidx = counter->counter_index; ni_tio_read_sw_save_reg()
1225 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0); ni_tio_read_sw_save_reg()
1226 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), ni_tio_read_sw_save_reg()
1238 val = read_register(counter, NITIO_SW_SAVE_REG(cidx)); ni_tio_read_sw_save_reg()
1239 if (val != read_register(counter, NITIO_SW_SAVE_REG(cidx))) ni_tio_read_sw_save_reg()
1240 val = read_register(counter, NITIO_SW_SAVE_REG(cidx)); ni_tio_read_sw_save_reg()
1250 struct ni_gpct *counter = s->private; ni_tio_insn_read() local
1251 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_insn_read()
1253 unsigned cidx = counter->counter_index; ni_tio_insn_read()
1273 static unsigned ni_tio_next_load_register(struct ni_gpct *counter) ni_tio_next_load_register() argument
1275 unsigned cidx = counter->counter_index; ni_tio_next_load_register()
1277 read_register(counter, NITIO_SHARED_STATUS_REG(cidx)); ni_tio_next_load_register()
1289 struct ni_gpct *counter = s->private; ni_tio_insn_write() local
1290 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_insn_write()
1292 unsigned cidx = counter->counter_index; ni_tio_insn_write()
1300 * Unsafe if counter is armed. ni_tio_insn_write()
1308 load_reg = ni_tio_next_load_register(counter); ni_tio_insn_write()
1309 write_register(counter, data[0], load_reg); ni_tio_insn_write()
1310 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx), ni_tio_insn_write()
1313 write_register(counter, counter_dev->regs[load_reg], load_reg); ni_tio_insn_write()
1317 write_register(counter, data[0], NITIO_LOADA_REG(cidx)); ni_tio_insn_write()
1321 write_register(counter, data[0], NITIO_LOADB_REG(cidx)); ni_tio_insn_write()
1330 void ni_tio_init_counter(struct ni_gpct *counter) ni_tio_init_counter() argument
1332 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_init_counter()
1333 unsigned cidx = counter->counter_index; ni_tio_init_counter()
1335 ni_tio_reset_count_and_disarm(counter); ni_tio_init_counter()
1337 /* initialize counter registers */ ni_tio_init_counter()
1339 write_register(counter, 0x0, NITIO_AUTO_INC_REG(cidx)); ni_tio_init_counter()
1341 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), ni_tio_init_counter()
1344 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0); ni_tio_init_counter()
1347 write_register(counter, 0x0, NITIO_LOADA_REG(cidx)); ni_tio_init_counter()
1350 write_register(counter, 0x0, NITIO_LOADB_REG(cidx)); ni_tio_init_counter()
1352 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0); ni_tio_init_counter()
1355 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0); ni_tio_init_counter()
1359 write_register(counter, 0x0, NITIO_GATE2_REG(cidx)); ni_tio_init_counter()
1362 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0); ni_tio_init_counter()
1364 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0); ni_tio_init_counter()
1370 void (*write_register)(struct ni_gpct *counter, ni_gpct_device_construct()
1373 unsigned (*read_register)(struct ni_gpct *counter, ni_gpct_device_construct()
1379 struct ni_gpct *counter; ni_gpct_device_construct() local
1396 counter_dev->counters = kcalloc(num_counters, sizeof(*counter), ni_gpct_device_construct()
1404 counter = &counter_dev->counters[i]; ni_gpct_device_construct()
1405 counter->counter_dev = counter_dev; ni_gpct_device_construct()
1406 spin_lock_init(&counter->lock); ni_gpct_device_construct()
1369 ni_gpct_device_construct(struct comedi_device *dev, void (*write_register)(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg), unsigned (*read_register)(struct ni_gpct *counter, enum ni_gpct_register reg), enum ni_gpct_variant variant, unsigned num_counters) ni_gpct_device_construct() argument
H A Dcomedi_8254.h3 * Generic 8254 timer/counter support
58 /* counter maps zero to 0x10000 */
68 * @divisor: divisor for single counter
69 * @divisor1: divisor loaded into first cascaded counter
70 * @divisor2: divisor loaded into second cascaded counter
71 * #next_div: next divisor for single counter
72 * @next_div1: next divisor to use for first cascaded counter
73 * @next_div2: next divisor to use for second cascaded counter
74 * @clock_src; current clock source for each counter (driver specific)
75 * @gate_src; current gate source for each counter (driver specific)
76 * @busy: flags used to indicate that a counter is "busy"
99 unsigned int comedi_8254_status(struct comedi_8254 *, unsigned int counter);
100 unsigned int comedi_8254_read(struct comedi_8254 *, unsigned int counter);
102 unsigned int counter, unsigned int val);
105 unsigned int counter, unsigned int mode);
107 unsigned int counter, unsigned int val, unsigned int mode);
119 unsigned int counter, bool busy);
H A Dcomedi_8254.c3 * Generic 8254 timer/counter support
24 * Description: Generic 8254 timer/counter support
62 * Writes an initial value to a counter.
67 * NOTE: The counter does not stop when it reaches zero. In Mode 0, 1, 4,
68 * and 5 the counter "wraps around" to the highest count, either 0xffff
70 * Modes 2 and 3 are periodic; the counter reloads itself with the initial
74 * Reads the current value from a counter.
77 * Reads the status of a counter.
87 * Calculates the divisor value needed for a single counter to generate
108 * Internally flags a counter as "busy". This is done to protect the
112 * the current value and write an initial value to a counter. A (*insn_config)
191 * comedi_8254_status - return the status of a counter
193 * @counter: the counter number
195 unsigned int comedi_8254_status(struct comedi_8254 *i8254, unsigned int counter) comedi_8254_status() argument
199 if (counter > 2) comedi_8254_status()
202 cmd = I8254_CTRL_READBACK_STATUS | I8254_CTRL_READBACK_SEL_CTR(counter); comedi_8254_status()
205 return __i8254_read(i8254, counter); comedi_8254_status()
210 * comedi_8254_read - read the current counter value
212 * @counter: the counter number
214 unsigned int comedi_8254_read(struct comedi_8254 *i8254, unsigned int counter) comedi_8254_read() argument
218 if (counter > 2) comedi_8254_read()
221 /* latch counter */ comedi_8254_read()
222 __i8254_write(i8254, I8254_CTRL_SEL_CTR(counter) | I8254_CTRL_LATCH, comedi_8254_read()
226 val = __i8254_read(i8254, counter); comedi_8254_read()
227 val |= (__i8254_read(i8254, counter) << 8); comedi_8254_read()
234 * comedi_8254_write - load a 16-bit initial counter value
236 * @counter: the counter number
240 unsigned int counter, unsigned int val) comedi_8254_write()
244 if (counter > 2) comedi_8254_write()
251 __i8254_write(i8254, byte, counter); comedi_8254_write()
253 __i8254_write(i8254, byte, counter); comedi_8254_write()
258 * comedi_8254_set_mode - set the mode of a counter
260 * @counter: the counter number
263 int comedi_8254_set_mode(struct comedi_8254 *i8254, unsigned int counter, comedi_8254_set_mode() argument
268 if (counter > 2) comedi_8254_set_mode()
273 byte = I8254_CTRL_SEL_CTR(counter) | /* select counter */ comedi_8254_set_mode()
283 * comedi_8254_load - program the mode and initial count of a counter
285 * @counter: the counter number
289 int comedi_8254_load(struct comedi_8254 *i8254, unsigned int counter, comedi_8254_load() argument
292 if (counter > 2) comedi_8254_load()
299 comedi_8254_set_mode(i8254, counter, mode); comedi_8254_load()
300 comedi_8254_write(i8254, counter, val); comedi_8254_load()
309 * @counter1: the counter number for the first divisor
310 * @counter2: the counter number for the second divisor
333 * Divisors are loaded second counter then first counter to comedi_8254_pacer_enable()
334 * avoid possible issues with the first counter expiring comedi_8254_pacer_enable()
335 * before the second counter is loaded. comedi_8254_pacer_enable()
349 /* masking is done since counter maps zero to 0x10000 */ comedi_8254_update_divisors()
475 * comedi_8254_set_busy - set/clear the "busy" flag for a given counter
477 * @counter: the counter number
481 unsigned int counter, bool busy) comedi_8254_set_busy()
483 if (counter < 3) comedi_8254_set_busy()
484 i8254->busy[counter] = busy; comedi_8254_set_busy()
620 * @osc_base: base time of the counter in ns
637 * @osc_base: base time of the counter in ns
663 MODULE_DESCRIPTION("Comedi: Generic 8254 timer/counter support");
239 comedi_8254_write(struct comedi_8254 *i8254, unsigned int counter, unsigned int val) comedi_8254_write() argument
480 comedi_8254_set_busy(struct comedi_8254 *i8254, unsigned int counter, bool busy) comedi_8254_set_busy() argument
H A Damplc_dio200.c70 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
77 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
81 * counter channel into data[1].
83 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
88 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
89 * connector. (N.B. for other values, the counter channel's CLKn
96 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
97 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
98 * the SK1 connector. This pin is shared by all three counter
101 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
105 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
112 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
113 * connector. (N.B. for other values, the counter channel's GATn
115 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
122 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
128 * same counter subdevice if n > 0, or the output of channel 2 on the
129 * preceding counter subdevice (see note 3) if n = 0.
132 * same counter subdevice if n = 2, or the inverted output of channel n+1
133 * on the preceding counter subdevice (see note 3) if n < 2.
135 * 3. The counter subdevices are connected in a ring, so the highest
136 * counter subdevice precedes the lowest.
H A Dni_tio_internal.h3 Header file for NI general purpose counter support code (ni_tio.c and
159 static inline void write_register(struct ni_gpct *counter, unsigned bits, write_register() argument
163 counter->counter_dev->write_register(counter, bits, reg); write_register()
166 static inline unsigned read_register(struct ni_gpct *counter, read_register() argument
170 return counter->counter_dev->read_register(counter, reg); read_register()
190 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter, ni_tio_set_bits_transient() argument
196 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_set_bits_transient()
203 write_register(counter, ni_tio_set_bits_transient()
214 static inline void ni_tio_set_bits(struct ni_gpct *counter, ni_tio_set_bits() argument
218 ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values, ni_tio_set_bits()
226 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter, ni_tio_get_soft_copy() argument
230 struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_get_soft_copy()
241 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
242 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
H A Damplc_dio200_pci.c72 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
79 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
83 * counter channel into data[1].
85 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
90 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
91 * connector. (N.B. for other values, the counter channel's CLKn
98 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
99 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
100 * the SK1 connector. This pin is shared by all three counter
111 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
115 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
122 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
123 * connector. (N.B. for other values, the counter channel's GATn
125 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
136 * 6. /GAT n, negated version of the counter channel's dedicated
138 * 7. OUT n-2, the non-inverted output of counter channel n-2
153 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
159 * same counter subdevice if n > 0, or the output of channel 2 on the
160 * preceding counter subdevice (see note 3) if n = 0.
163 * same counter subdevice if n = 2, or the inverted output of channel n+1
164 * on the preceding counter subdevice (see note 3) if n < 2.
166 * 3. The counter subdevices are connected in a ring, so the highest
167 * counter subdevice precedes the lowest.
H A Ddas16m1.c125 struct comedi_8254 *counter; member in struct:das16m1_private_struct
128 /* initial value in lower half of hardware conversion counter,
130 * counter yet (loaded by first sample conversion) */
264 * Initialize lower half of hardware counter, used to determine how das16m1_cmd_exec()
265 * many samples are in fifo. Value doesn't actually load into counter das16m1_cmd_exec()
266 * until counter's next clock (the next a/d conversion). das16m1_cmd_exec()
268 comedi_8254_set_mode(devpriv->counter, 1, I8254_MODE2 | I8254_BINARY); das16m1_cmd_exec()
269 comedi_8254_write(devpriv->counter, 1, 0); das16m1_cmd_exec()
272 * Remember current reading of counter so we know when counter has das16m1_cmd_exec()
275 devpriv->initial_hw_count = comedi_8254_read(devpriv->counter, 1); das16m1_cmd_exec()
286 /* enable interrupts and set internal pacer counter mode and counts */ das16m1_cmd_exec()
411 hw_counter = comedi_8254_read(devpriv->counter, 1); das16m1_handler()
412 /* make sure hardware counter reading is not bogus due to initial value das16m1_handler()
418 * 16 bit hardware counter is initialized with value of zero (which really das16m1_handler()
419 * means 0x1000). The counter decrements by one on each conversion das16m1_handler()
420 * (when the counter decrements from zero it goes to 0xffff). num_samples das16m1_handler()
422 * hardware counter. Work it out, and this is what you get. */ das16m1_handler()
561 devpriv->counter = comedi_8254_init(dev->iobase + DAS16M1_8254_FIRST, das16m1_attach()
563 if (!devpriv->counter) das16m1_attach()
629 kfree(devpriv->counter); das16m1_detach()
H A Dni_660x.c18 * Description: National Instruments 660x counter/timer boards
303 /* kind of ENABLE for the second counter */
620 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, ni_gpct_write_register() argument
623 struct comedi_device *dev = counter->counter_dev->dev; ni_gpct_write_register()
625 unsigned chip = counter->chip_index; ni_gpct_write_register()
630 static unsigned ni_gpct_read_register(struct ni_gpct *counter, ni_gpct_read_register() argument
633 struct comedi_device *dev = counter->counter_dev->dev; ni_gpct_read_register()
635 unsigned chip = counter->chip_index; ni_gpct_read_register()
643 *counter) mite_ring()
645 unsigned chip = counter->chip_index; mite_ring()
647 return priv->mite_rings[chip][counter->counter_index]; mite_ring()
652 struct ni_gpct *counter) ni_660x_set_dma_channel()
655 unsigned chip = counter->chip_index; ni_660x_set_dma_channel()
662 dma_select_bits(mite_channel, counter->counter_index); ni_660x_set_dma_channel()
672 struct ni_gpct *counter) ni_660x_unset_dma_channel()
675 unsigned chip = counter->chip_index; ni_660x_unset_dma_channel()
691 struct ni_gpct *counter, ni_660x_request_mite_channel()
699 BUG_ON(counter->mite_chan); ni_660x_request_mite_channel()
701 mite_ring(devpriv, counter)); ni_660x_request_mite_channel()
705 "failed to reserve mite dma channel for counter\n"); ni_660x_request_mite_channel()
709 ni_tio_set_mite_channel(counter, mite_chan); ni_660x_request_mite_channel()
710 ni_660x_set_dma_channel(dev, mite_chan->channel, counter); ni_660x_request_mite_channel()
716 struct ni_gpct *counter) ni_660x_release_mite_channel()
722 if (counter->mite_chan) { ni_660x_release_mite_channel()
723 struct mite_channel *mite_chan = counter->mite_chan; ni_660x_release_mite_channel()
725 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter); ni_660x_release_mite_channel()
726 ni_tio_set_mite_channel(counter, NULL); ni_660x_release_mite_channel()
734 struct ni_gpct *counter = s->private; ni_660x_cmd() local
737 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT); ni_660x_cmd()
740 "no dma channel available for use by counter\n"); ni_660x_cmd()
743 ni_tio_acknowledge(counter); ni_660x_cmd()
750 struct ni_gpct *counter = s->private; ni_660x_cancel() local
753 retval = ni_tio_cancel(counter); ni_660x_cancel()
754 ni_660x_release_mite_channel(dev, counter); ni_660x_cancel()
777 struct ni_gpct *counter = s->private; ni_660x_handle_gpct_interrupt() local
779 ni_tio_handle_interrupt(counter, s); ni_660x_handle_gpct_interrupt()
808 struct ni_gpct *counter = s->private; ni_660x_input_poll() local
813 mite_sync_input_dma(counter->mite_chan, s); ni_660x_input_poll()
822 struct ni_gpct *counter = s->private; ni_660x_buf_change() local
825 ret = mite_buf_change(mite_ring(devpriv, counter), s); ni_660x_buf_change()
1151 /* to be safe, set counterswap bits on tio chips after all the counter ni_660x_auto_attach()
640 mite_ring(struct ni_660x_private *priv, struct ni_gpct *counter) mite_ring() argument
650 ni_660x_set_dma_channel(struct comedi_device *dev, unsigned mite_channel, struct ni_gpct *counter) ni_660x_set_dma_channel() argument
670 ni_660x_unset_dma_channel(struct comedi_device *dev, unsigned mite_channel, struct ni_gpct *counter) ni_660x_unset_dma_channel() argument
690 ni_660x_request_mite_channel(struct comedi_device *dev, struct ni_gpct *counter, enum comedi_io_direction direction) ni_660x_request_mite_channel() argument
715 ni_660x_release_mite_channel(struct comedi_device *dev, struct ni_gpct *counter) ni_660x_release_mite_channel() argument
H A Dni_tio.h3 Header file for NI general purpose counter support code (ni_tio.c)
118 void (*write_register)(struct ni_gpct *counter, unsigned bits,
120 unsigned (*read_register)(struct ni_gpct *counter,
H A Dquatech_daqp_cs.c273 int counter = 10000; daqp_ai_insn_read() local
304 while (--counter daqp_ai_insn_read()
307 if (!counter) { daqp_ai_insn_read()
334 /* This function converts ns nanoseconds to a counter value suitable
336 * which with its 24-bit counter, allows values up to 84 seconds.
450 int counter; daqp_ai_cmd() local
482 counter = daqp_ns_to_timer(&cmd->convert_arg, cmd->flags); daqp_ai_cmd()
483 outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW); daqp_ai_cmd()
484 outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID); daqp_ai_cmd()
485 outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH); daqp_ai_cmd()
488 counter = daqp_ns_to_timer(&cmd->scan_begin_arg, cmd->flags); daqp_ai_cmd()
489 outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW); daqp_ai_cmd()
490 outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID); daqp_ai_cmd()
491 outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH); daqp_ai_cmd()
610 counter = 100; daqp_ai_cmd()
611 while (--counter daqp_ai_cmd()
614 if (!counter) { daqp_ai_cmd()
H A Daddi_tcw.h5 * Following are the generic definitions for the ADDI-DATA timer/counter/
/linux-4.1.27/arch/metag/include/asm/
H A Datomic_lock1.h13 return (v)->counter; atomic_read()
18 * possible race, as it reads the counter twice:
22 * ret = v->counter (non-zero)
23 * if (ret != u) v->counter = 0
24 * v->counter += 1 (counter set to 1)
35 v->counter = i; atomic_set()
47 v->counter c_op i; \
58 result = v->counter; \
61 v->counter = result; \
82 v->counter &= ~mask; atomic_clear_mask()
92 v->counter |= mask; atomic_set_mask()
102 ret = v->counter; atomic_cmpxchg()
105 v->counter = new; atomic_cmpxchg()
112 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
120 ret = v->counter; __atomic_add_unless()
123 v->counter += a; __atomic_add_unless()
136 ret = v->counter - 1; atomic_sub_if_positive()
139 v->counter = ret; atomic_sub_if_positive()
H A Datomic_lnkget.h6 #define atomic_set(v, i) ((v)->counter = (i))
25 : "da" (&v->counter)); atomic_read()
44 : "da" (&v->counter), "bd" (i) \
64 : "da" (&v->counter), "bd" (i) \
94 : "da" (&v->counter), "bd" (~mask) atomic_clear_mask()
111 : "da" (&v->counter), "bd" (mask) atomic_set_mask()
132 : "da" (&v->counter), "bd" (old), "da" (new) atomic_cmpxchg()
152 : "da" (&v->counter), "da" (new) atomic_xchg()
176 : "da" (&v->counter), "bd" (u), "bd" (a) __atomic_add_unless()
199 : "da" (&v->counter), "bd" (i) atomic_sub_if_positive()
/linux-4.1.27/mm/
H A Dpage_counter.c16 * page_counter_cancel - take pages out of the local counter
17 * @counter: counter
20 void page_counter_cancel(struct page_counter *counter, unsigned long nr_pages) page_counter_cancel() argument
24 new = atomic_long_sub_return(nr_pages, &counter->count); page_counter_cancel()
31 * @counter: counter
34 * NOTE: This does not consider any configured counter limits.
36 void page_counter_charge(struct page_counter *counter, unsigned long nr_pages) page_counter_charge() argument
40 for (c = counter; c; c = c->parent) { page_counter_charge()
55 * @counter: counter
57 * @fail: points first counter to hit its limit, if any
59 * Returns 0 on success, or -ENOMEM and @fail if the counter or one of
62 int page_counter_try_charge(struct page_counter *counter, page_counter_try_charge() argument
68 for (c = counter; c; c = c->parent) { page_counter_try_charge()
82 * counter has changed and retries. page_counter_try_charge()
105 for (c = counter; c != *fail; c = c->parent) page_counter_try_charge()
113 * @counter: counter
116 void page_counter_uncharge(struct page_counter *counter, unsigned long nr_pages) page_counter_uncharge() argument
120 for (c = counter; c; c = c->parent) page_counter_uncharge()
126 * @counter: counter
130 * counter already exceeds the specified limit.
132 * The caller must serialize invocations on the same counter.
134 int page_counter_limit(struct page_counter *counter, unsigned long limit) page_counter_limit() argument
142 * below the concurrently-changing counter value. page_counter_limit()
149 * modified counter and retry. page_counter_limit()
151 count = atomic_long_read(&counter->count); page_counter_limit()
156 old = xchg(&counter->limit, limit); page_counter_limit()
158 if (atomic_long_read(&counter->count) <= count) page_counter_limit()
161 counter->limit = old; page_counter_limit()
167 * page_counter_memparse - memparse() for page counter limits
H A Dhugetlb_cgroup.c25 * the counter to account for hugepages from hugetlb.
113 struct page_counter *counter; hugetlb_cgroup_move_parent() local
132 counter = &h_cg->hugepage[idx]; hugetlb_cgroup_move_parent()
133 /* Take the pages off the local counter */ hugetlb_cgroup_move_parent()
134 page_counter_cancel(counter, nr_pages); hugetlb_cgroup_move_parent()
169 struct page_counter *counter; hugetlb_cgroup_charge_cgroup() local
189 ret = page_counter_try_charge(&h_cg->hugepage[idx], nr_pages, &counter); hugetlb_cgroup_charge_cgroup()
250 struct page_counter *counter; hugetlb_cgroup_read_u64() local
253 counter = &h_cg->hugepage[MEMFILE_IDX(cft->private)]; hugetlb_cgroup_read_u64()
257 return (u64)page_counter_read(counter) * PAGE_SIZE; hugetlb_cgroup_read_u64()
259 return (u64)counter->limit * PAGE_SIZE; hugetlb_cgroup_read_u64()
261 return (u64)counter->watermark * PAGE_SIZE; hugetlb_cgroup_read_u64()
263 return counter->failcnt; hugetlb_cgroup_read_u64()
305 struct page_counter *counter; hugetlb_cgroup_reset() local
308 counter = &h_cg->hugepage[MEMFILE_IDX(of_cft(of)->private)]; hugetlb_cgroup_reset()
312 page_counter_reset_watermark(counter); hugetlb_cgroup_reset()
315 counter->failcnt = 0; hugetlb_cgroup_reset()
/linux-4.1.27/arch/arm/include/asm/
H A Datomic.h30 #define atomic_read(v) ACCESS_ONCE((v)->counter)
31 #define atomic_set(v,i) (((v)->counter) = (i))
47 prefetchw(&v->counter); \
54 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
55 : "r" (&v->counter), "Ir" (i) \
66 prefetchw(&v->counter); \
74 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
75 : "r" (&v->counter), "Ir" (i) \
89 prefetchw(&ptr->counter); atomic_cmpxchg()
97 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter) atomic_cmpxchg()
98 : "r" (&ptr->counter), "Ir" (old), "r" (new) atomic_cmpxchg()
113 prefetchw(&v->counter); __atomic_add_unless()
124 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter) __atomic_add_unless()
125 : "r" (&v->counter), "r" (u), "r" (a) __atomic_add_unless()
146 v->counter c_op i; \
157 v->counter c_op i; \
158 val = v->counter; \
170 ret = v->counter; atomic_cmpxchg()
172 v->counter = new; atomic_cmpxchg()
201 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
216 long long counter; member in struct:__anon149
229 : "r" (&v->counter), "Qo" (v->counter) atomic64_read()
239 : "=Qo" (v->counter) atomic64_set()
240 : "r" (&v->counter), "r" (i) atomic64_set()
251 : "r" (&v->counter), "Qo" (v->counter) atomic64_read()
261 prefetchw(&v->counter); atomic64_set()
267 : "=&r" (tmp), "=Qo" (v->counter) atomic64_set()
268 : "r" (&v->counter), "r" (i) atomic64_set()
279 prefetchw(&v->counter); \
287 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
288 : "r" (&v->counter), "r" (i) \
299 prefetchw(&v->counter); \
308 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
309 : "r" (&v->counter), "r" (i) \
335 prefetchw(&ptr->counter); atomic64_cmpxchg()
344 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter) atomic64_cmpxchg()
345 : "r" (&ptr->counter), "r" (old), "r" (new) atomic64_cmpxchg()
360 prefetchw(&ptr->counter); atomic64_xchg()
367 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter) atomic64_xchg()
368 : "r" (&ptr->counter), "r" (new) atomic64_xchg()
382 prefetchw(&v->counter); atomic64_dec_if_positive()
394 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) atomic64_dec_if_positive()
395 : "r" (&v->counter) atomic64_dec_if_positive()
410 prefetchw(&v->counter); atomic64_add_unless()
424 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter) atomic64_add_unless()
425 : "r" (&v->counter), "r" (u), "r" (a) atomic64_add_unless()
H A Dmmu.h22 #define ASID(mm) ((unsigned int)((mm)->context.id.counter & ~ASID_MASK))
/linux-4.1.27/arch/x86/kernel/cpu/
H A Dperfctr-watchdog.c46 /* returns the bit offset of the performance counter register */ nmi_perfctr_msr_to_bit()
98 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter) avail_to_resrv_perfctr_nmi_bit() argument
100 BUG_ON(counter > NMI_MAX_COUNTER_BITS); avail_to_resrv_perfctr_nmi_bit()
102 return !test_bit(counter, perfctr_nmi_owner); avail_to_resrv_perfctr_nmi_bit()
108 unsigned int counter; reserve_perfctr_nmi() local
110 counter = nmi_perfctr_msr_to_bit(msr); reserve_perfctr_nmi()
112 if (counter > NMI_MAX_COUNTER_BITS) reserve_perfctr_nmi()
115 if (!test_and_set_bit(counter, perfctr_nmi_owner)) reserve_perfctr_nmi()
123 unsigned int counter; release_perfctr_nmi() local
125 counter = nmi_perfctr_msr_to_bit(msr); release_perfctr_nmi()
127 if (counter > NMI_MAX_COUNTER_BITS) release_perfctr_nmi()
130 clear_bit(counter, perfctr_nmi_owner); release_perfctr_nmi()
136 unsigned int counter; reserve_evntsel_nmi() local
138 counter = nmi_evntsel_msr_to_bit(msr); reserve_evntsel_nmi()
140 if (counter > NMI_MAX_COUNTER_BITS) reserve_evntsel_nmi()
143 if (!test_and_set_bit(counter, evntsel_nmi_owner)) reserve_evntsel_nmi()
151 unsigned int counter; release_evntsel_nmi() local
153 counter = nmi_evntsel_msr_to_bit(msr); release_evntsel_nmi()
155 if (counter > NMI_MAX_COUNTER_BITS) release_evntsel_nmi()
158 clear_bit(counter, evntsel_nmi_owner); release_evntsel_nmi()
H A Dperf_event.h74 #define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */
130 INTEL_EXCL_UNUSED = 0, /* counter is unused */
131 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
132 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
167 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
177 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
222 * manage exclusive counter access between hyperthread
255 * The overlap flag marks event constraints with overlapping counter
256 * masks. This is the case if the counter mask of such an event is not
257 * a subset of any other counter mask of a constraint with an equal or
264 * The event scheduler may not select the correct counter in the first
268 * events to select for counter rescheduling.
273 * and its counter masks must be kept at a minimum.
287 * filter mask to validate fixed counter events.
382 * to enable blacklisting of events using a counter bitmask
446 * PMU supports separate counter range for writing
632 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
633 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
/linux-4.1.27/arch/blackfin/include/asm/
H A Datomic.h25 #define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
27 #define atomic_add_return(i, v) __raw_atomic_update_asm(&(v)->counter, i)
28 #define atomic_sub_return(i, v) __raw_atomic_update_asm(&(v)->counter, -(i))
30 #define atomic_clear_mask(m, v) __raw_atomic_clear_asm(&(v)->counter, m)
31 #define atomic_set_mask(m, v) __raw_atomic_set_asm(&(v)->counter, m)
H A Dtime.h18 * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
19 * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
/linux-4.1.27/arch/metag/kernel/perf/
H A Dperf_event.h2 * Meta performance counter support.
17 /* For performance counter definitions */
24 * Each counter consists of the counter id, hardware thread id, and the count
25 * itself; each counter can be assigned to multiple hardware threads at any
30 * Newer cores can store an arbitrary 24-bit number in the counter, whereas
31 * older cores will clear the counter bits on write.
33 * We also have a pseudo-counter in the form of the thread active cycles
34 * counter (which, incidentally, is also bound to
45 * @pmu_lock: a perf counter lock
62 * @enable: enable a counter
63 * @disable: disable a counter
64 * @read: read the value of a counter
65 * @write: write a value to a counter
66 * @event_map: kernel event to counter event id map
67 * @cache_events: kernel cache counter to core cache counter map
68 * @max_period: maximum value of the counter before overflow
71 * @reserve_mutex: counter reservation mutex
H A Dperf_event.c2 * Meta performance counter support.
96 * Bit 16 on HWSTATMETA is the interrupt for performance counter 0; reserve_pmu_hardware()
97 * similarly, 17 is the interrupt for performance counter 1. reserve_pmu_hardware()
98 * We can't (yet) interrupt on the cycle counter, because it's a reserve_pmu_hardware()
196 * If this counter is chained, it may be that the previous counter metag_pmu_event_update()
200 * add the delta (new - prev) to the generic counter atomically. metag_pmu_event_update()
213 * Calculate the delta and add it to the counter. metag_pmu_event_update()
279 * counter was 'stopped' we merely disabled the IRQ. If we don't reset metag_pmu_start()
283 * interrupt, as the performance counter resets to zero on write metag_pmu_start()
297 * We should always update the counter on stop; see comment above metag_pmu_stop()
324 /* Check whether we have a spare counter */ metag_pmu_add()
336 /* Make sure the counter is disabled */ metag_pmu_add()
387 /* Core counter specific functions */
583 * counter width. This way, the new counter value should be less _hw_perf_event_init()
608 * Check if we're enabling the instruction counter (index of metag_pmu_enable_counter()
613 "invalid configuration (%d) for counter (%d)\n", metag_pmu_enable_counter()
625 * nibble to the correct counter register. metag_pmu_enable_counter()
655 * Cores supporting overflow interrupts may have had the counter metag_pmu_enable_counter()
661 * Older cores reset the counter on write, so prev_count needs metag_pmu_enable_counter()
678 * The cycle counter can't be disabled per se, as it's a hardware metag_pmu_disable_counter()
680 * is the counter we're attempting to disable. metag_pmu_disable_counter()
686 * The counter value _should_ have been read prior to disabling, metag_pmu_disable_counter()
734 * counter itself. Also , we should bound the value to 24-bits. metag_pmu_write_counter()
760 u32 counter = 0; metag_pmu_counter_overflow() local
764 * interrupt while we disable this counter. However, we don't want metag_pmu_counter_overflow()
765 * to flag the counter as free metag_pmu_counter_overflow()
768 counter = metag_in32(PERF_COUNT(idx)); metag_pmu_counter_overflow()
769 metag_out32((counter & 0x00ffffff), PERF_COUNT(idx)); metag_pmu_counter_overflow()
778 * Enable the counter again once core overflow processing has metag_pmu_counter_overflow()
779 * completed. Note the counter value may have been modified while it was metag_pmu_counter_overflow()
784 counter = (counter & 0xff000000) | metag_pmu_counter_overflow()
786 metag_out32(counter, PERF_COUNT(idx)); metag_pmu_counter_overflow()
836 pr_info("no hardware counter support available\n"); init_hw_perf_events()
/linux-4.1.27/arch/alpha/include/asm/
H A Dlocal.h32 :"=&r" (temp), "=m" (l->a.counter), "=&r" (result) local_add_return()
33 :"Ir" (i), "m" (l->a.counter) : "memory"); local_add_return()
49 :"=&r" (temp), "=m" (l->a.counter), "=&r" (result) local_sub_return()
50 :"Ir" (i), "m" (l->a.counter) : "memory"); local_sub_return()
55 (cmpxchg_local(&((l)->a.counter), (o), (n)))
56 #define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
96 #define __local_inc(l) ((l)->a.counter++)
97 #define __local_dec(l) ((l)->a.counter++)
98 #define __local_add(i,l) ((l)->a.counter+=(i))
99 #define __local_sub(i,l) ((l)->a.counter-=(i))
H A Datomic.h20 #define atomic_read(v) ACCESS_ONCE((v)->counter)
21 #define atomic64_read(v) ACCESS_ONCE((v)->counter)
23 #define atomic_set(v,i) ((v)->counter = (i))
24 #define atomic64_set(v,i) ((v)->counter = (i))
44 :"=&r" (temp), "=m" (v->counter) \
45 :"Ir" (i), "m" (v->counter)); \
62 :"=&r" (temp), "=m" (v->counter), "=&r" (result) \
63 :"Ir" (i), "m" (v->counter) : "memory"); \
80 :"=&r" (temp), "=m" (v->counter) \
81 :"Ir" (i), "m" (v->counter)); \
98 :"=&r" (temp), "=m" (v->counter), "=&r" (result) \
99 :"Ir" (i), "m" (v->counter) : "memory"); \
119 #define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
120 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
122 #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
123 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
H A Dtimex.h14 * Standard way to access the cycle counter.
/linux-4.1.27/arch/mips/include/asm/
H A Dlocal.h44 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) local_add_return()
45 : "Ir" (i), "m" (l->a.counter) local_add_return()
58 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) local_add_return()
59 : "Ir" (i), "m" (l->a.counter) local_add_return()
65 result = l->a.counter; local_add_return()
67 l->a.counter = result; local_add_return()
89 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) local_sub_return()
90 : "Ir" (i), "m" (l->a.counter) local_sub_return()
103 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) local_sub_return()
104 : "Ir" (i), "m" (l->a.counter) local_sub_return()
110 result = l->a.counter; local_sub_return()
112 l->a.counter = result; local_sub_return()
120 ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
192 #define __local_inc(l) ((l)->a.counter++)
193 #define __local_dec(l) ((l)->a.counter++)
194 #define __local_add(i, l) ((l)->a.counter+=(i))
195 #define __local_sub(i, l) ((l)->a.counter-=(i))
H A Datomic.h33 #define atomic_read(v) ACCESS_ONCE((v)->counter)
42 #define atomic_set(v, i) ((v)->counter = (i))
57 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
69 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
76 v->counter c_op i; \
100 "+" GCC_OFF_SMALL_ASM() (v->counter) \
113 "+" GCC_OFF_SMALL_ASM() (v->counter) \
122 result = v->counter; \
124 v->counter = result; \
174 "+" GCC_OFF_SMALL_ASM() (v->counter) atomic_sub_if_positive()
175 : "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) atomic_sub_if_positive()
193 "+" GCC_OFF_SMALL_ASM() (v->counter) atomic_sub_if_positive()
199 result = v->counter; atomic_sub_if_positive()
202 v->counter = result; atomic_sub_if_positive()
211 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
212 #define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
314 #define atomic64_read(v) ACCESS_ONCE((v)->counter)
321 #define atomic64_set(v, i) ((v)->counter = (i))
336 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
348 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
355 v->counter c_op i; \
379 "+" GCC_OFF_SMALL_ASM() (v->counter) \
392 "=" GCC_OFF_SMALL_ASM() (v->counter) \
393 : "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
402 result = v->counter; \
404 v->counter = result; \
455 "=" GCC_OFF_SMALL_ASM() (v->counter) atomic64_sub_if_positive()
456 : "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) atomic64_sub_if_positive()
474 "+" GCC_OFF_SMALL_ASM() (v->counter) atomic64_sub_if_positive()
480 result = v->counter; atomic64_sub_if_positive()
483 v->counter = result; atomic64_sub_if_positive()
493 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
494 #define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
H A Dtimex.h30 * Standard way to access the cycle counter.
44 * cycle counter is read in the exact moment that it is matching the
77 return 0; /* no usable counter */ get_cycles()
/linux-4.1.27/arch/powerpc/include/asm/
H A Dlocal.h33 : "r" (a), "r" (&(l->a.counter)) local_add_return()
52 : "r" (a), "r" (&(l->a.counter)) local_sub_return()
69 : "r" (&(l->a.counter)) local_inc_return()
96 : "r" (&(l->a.counter)) local_dec_return()
103 (cmpxchg_local(&((l)->a.counter), (o), (n)))
104 #define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
130 : "r" (&(l->a.counter)), "r" (a), "r" (u) local_add_unless()
159 : "r" (&(l->a.counter)) local_dec_if_positive()
170 #define __local_inc(l) ((l)->a.counter++)
171 #define __local_dec(l) ((l)->a.counter++)
172 #define __local_add(i,l) ((l)->a.counter+=(i))
173 #define __local_sub(i,l) ((l)->a.counter-=(i))
H A Datomic.h19 __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter)); atomic_read()
26 __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i)); atomic_set()
40 : "=&r" (t), "+m" (v->counter) \
41 : "r" (a), "r" (&v->counter) \
59 : "r" (a), "r" (&v->counter) \
86 : "=&r" (t), "+m" (v->counter) atomic_inc()
87 : "r" (&v->counter) atomic_inc()
104 : "r" (&v->counter) atomic_inc_return()
130 : "=&r" (t), "+m" (v->counter) atomic_dec()
131 : "r" (&v->counter) atomic_dec()
148 : "r" (&v->counter) atomic_dec_return()
154 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
155 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
183 : "r" (&v->counter), "r" (a), "r" (u) __atomic_add_unless()
213 : "r" (&v->counter) atomic_inc_not_zero()
244 : "r" (&v->counter) atomic_dec_if_positive()
259 __asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter)); atomic64_read()
266 __asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i)); atomic64_set()
279 : "=&r" (t), "+m" (v->counter) \
280 : "r" (a), "r" (&v->counter) \
297 : "r" (a), "r" (&v->counter) \
323 : "=&r" (t), "+m" (v->counter) atomic64_inc()
324 : "r" (&v->counter) atomic64_inc()
340 : "r" (&v->counter) atomic64_inc_return()
365 : "=&r" (t), "+m" (v->counter) atomic64_dec()
366 : "r" (&v->counter) atomic64_dec()
382 : "r" (&v->counter) atomic64_dec_return()
409 : "r" (&v->counter) atomic64_dec_if_positive()
415 #define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
416 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
443 : "r" (&v->counter), "r" (a), "r" (u) atomic64_add_unless()
472 : "r" (&v->counter) atomic64_inc_not_zero()
H A Dmutex.h22 : "r" (&v->counter), "r" (old), "r" (new) __mutex_cmpxchg_lock()
40 : "r" (&v->counter) __mutex_dec_return_lock()
58 : "r" (&v->counter) __mutex_inc_return_unlock()
H A Dtimex.h25 * For the "cycle" counter we use the timebase lower half. get_cycles()
H A Dimmap_qe.h118 __be16 gtcnr1; /* Timer 1 counter */
119 __be16 gtcnr2; /* Timer 2 counter */
126 __be16 gtcnr3; /* Timer 3 counter */
127 __be16 gtcnr4; /* Timer 4 counter */
173 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
174 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
175 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
176 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
177 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
178 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
179 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
180 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
193 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
194 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
195 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
196 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
197 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
198 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
199 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
200 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
288 __be32 urtry; /* UCC retry counter register */
/linux-4.1.27/arch/sparc/include/asm/
H A Datomic_64.h17 #define atomic_read(v) ACCESS_ONCE((v)->counter)
18 #define atomic64_read(v) ACCESS_ONCE((v)->counter)
20 #define atomic_set(v, i) (((v)->counter) = i)
21 #define atomic64_set(v, i) (((v)->counter) = i)
72 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
73 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
91 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
92 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
H A Dtimex_64.h13 /* Getting on the cycle counter on sparc64. */
H A Dtimer_32.h23 /* The counter timer register has the value offset by 9 bits.
25 * When a counter reaches the value in the corresponding limit register,
26 * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200).
H A Dcpudata_32.h17 unsigned int counter; member in struct:__anon2679
H A Datomic_32.h29 #define atomic_read(v) ACCESS_ONCE((v)->counter)
H A Dpil.h17 * interrupts. Profile counter overflow interrupts arrive at level
H A Dspinlock_32.h69 * | 24-bit counter | wlock | arch_rwlock_t
74 * counter. For a writer, if he successfully acquires the wlock,
75 * but counter is non-zero, he has to release the lock and wait,
76 * till both counter and wlock are zero.
/linux-4.1.27/arch/tile/include/asm/
H A Datomic_64.h27 #define atomic_set(v, i) ((v)->counter = (i))
37 __insn_fetchadd4((void *)&v->counter, i); atomic_add()
44 val = __insn_fetchadd4((void *)&v->counter, i) + i; atomic_add_return()
51 int guess, oldval = v->counter; __atomic_add_unless()
56 oldval = cmpxchg(&v->counter, guess, guess + a); __atomic_add_unless()
65 #define atomic64_read(v) ((v)->counter)
66 #define atomic64_set(v, i) ((v)->counter = (i))
70 __insn_fetchadd((void *)&v->counter, i); atomic64_add()
77 val = __insn_fetchadd((void *)&v->counter, i) + i; atomic64_add_return()
84 long guess, oldval = v->counter; atomic64_add_unless()
89 oldval = cmpxchg(&v->counter, guess, guess + a); atomic64_add_unless()
H A Datomic_32.h34 _atomic_xchg_add(&v->counter, i); atomic_add()
47 return _atomic_xchg_add(&v->counter, i) + i; atomic_add_return()
62 return _atomic_xchg_add_unless(&v->counter, a, u); __atomic_add_unless()
77 _atomic_xchg(&v->counter, n); atomic_set()
83 long long counter; member in struct:__anon2797
101 return _atomic64_xchg_add((long long *)&v->counter, 0); atomic64_read()
113 _atomic64_xchg_add(&v->counter, i); atomic64_add()
126 return _atomic64_xchg_add(&v->counter, i) + i; atomic64_add_return()
142 return _atomic64_xchg_add_unless(&v->counter, a, u) != u; atomic64_add_unless()
157 _atomic64_xchg(&v->counter, n); atomic64_set()
H A Datomic.h37 return ACCESS_ONCE(v->counter); atomic_read()
125 return xchg(&v->counter, n); atomic_xchg()
139 return cmpxchg(&v->counter, o, n); atomic_cmpxchg()
171 return xchg64(&v->counter, n); atomic64_xchg()
186 return cmpxchg64(&v->counter, o, n); atomic64_cmpxchg()
/linux-4.1.27/arch/microblaze/include/asm/
H A Datomic.h18 res = v->counter - 1; atomic_dec_if_positive()
20 v->counter = res; atomic_dec_if_positive()
H A Dmodule.h29 typedef struct { volatile int counter; } module_t; member in struct:__anon1849
/linux-4.1.27/arch/sh/include/asm/
H A Datomic-irq.h18 v->counter c_op i; \
28 temp = v->counter; \
30 v->counter = temp; \
50 v->counter &= ~mask; atomic_clear_mask()
59 v->counter |= mask; atomic_set_mask()
H A Datomic.h17 #define atomic_read(v) ACCESS_ONCE((v)->counter)
18 #define atomic_set(v,i) ((v)->counter = (i))
38 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
39 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
H A Datomic-llsc.h29 : "r" (i), "r" (&v->counter) \
45 : "r" (i), "r" (&v->counter) \
70 : "r" (~mask), "r" (&v->counter) atomic_clear_mask()
84 : "r" (mask), "r" (&v->counter) atomic_set_mask()
H A Dmutex-llsc.h32 : "r" (&(count)->counter) __mutex_fastpath_lock()
50 : "r" (&(count)->counter) __mutex_fastpath_lock_retval()
70 : "r" (&(count)->counter) __mutex_fastpath_unlock()
104 : "r" (&count->counter) __mutex_fastpath_trylock()
/linux-4.1.27/arch/x86/oprofile/
H A Dop_x86_model.h59 static inline void op_x86_warn_in_use(int counter) op_x86_warn_in_use() argument
62 * The warning indicates an already running counter. If op_x86_warn_in_use()
64 * performance counter on your platform to monitor the desired op_x86_warn_in_use()
65 * event. Delete counter #%d from the desired event by editing op_x86_warn_in_use()
67 * cannot be monitored by any other counter, contact your op_x86_warn_in_use()
70 pr_warning("oprofile: counter #%d on cpu #%d may already be used\n", op_x86_warn_in_use()
71 counter, smp_processor_id()); op_x86_warn_in_use()
74 static inline void op_x86_warn_reserved(int counter) op_x86_warn_reserved() argument
76 pr_warning("oprofile: counter #%d is already reserved\n", counter); op_x86_warn_reserved()
H A Dop_model_ppro.c84 * counter width: ppro_setup_ctrs()
148 * might have caught a *second* counter just after overflowing ppro_check_ctrs()
149 * the interrupt for this counter then arrives ppro_check_ctrs()
150 * and we don't find a counter that's overflowed, so we ppro_check_ctrs()
/linux-4.1.27/include/asm-generic/
H A Datomic.h2 * Generic C implementation of atomic counter operations. Usable on
47 c = v->counter; \
48 while ((old = cmpxchg(&v->counter, c, c c_op i)) != c) \
57 c = v->counter; \
58 while ((old = cmpxchg(&v->counter, c, c c_op i)) != c) \
74 v->counter = v->counter c_op i; \
85 ret = (v->counter = v->counter c_op i); \
129 #define atomic_read(v) ACCESS_ONCE((v)->counter)
139 #define atomic_set(v, i) (((v)->counter) = (i))
175 #define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
176 #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
H A Dtimex.h5 * If you have a cycle counter, return the value here.
/linux-4.1.27/arch/avr32/include/asm/
H A Datomic.h22 #define atomic_read(v) ACCESS_ONCE((v)->counter)
23 #define atomic_set(v, i) (((v)->counter) = i)
37 : "=&r" (result), "=o" (v->counter) \
38 : "m" (v->counter), #asm_con (i) \
117 : "=&r"(tmp), "=o"(v->counter) __atomic_add_unless()
118 : "m"(v->counter), "rKs21"(-a), "rKs21"(u) __atomic_add_unless()
131 : "=&r"(tmp), "=o"(v->counter) __atomic_add_unless()
132 : "m"(v->counter), "r"(a), "ir"(u) __atomic_add_unless()
162 : "=&r"(result), "=o"(v->counter) atomic_sub_if_positive()
163 : "m"(v->counter), "ir"(i) atomic_sub_if_positive()
169 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
170 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
/linux-4.1.27/arch/ia64/include/asm/
H A Datomic.h24 #define atomic_read(v) ACCESS_ONCE((v)->counter)
25 #define atomic64_read(v) ACCESS_ONCE((v)->counter)
27 #define atomic_set(v,i) (((v)->counter) = (i))
28 #define atomic64_set(v,i) (((v)->counter) = (i))
58 ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
70 ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
102 ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
114 ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
118 #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
119 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
122 (cmpxchg(&((v)->counter), old, new))
123 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
/linux-4.1.27/tools/perf/
H A Dbuiltin-stat.c13 Performance counter stats for './hackbench 10':
71 static void print_counter_aggr(struct perf_evsel *counter, char *prefix);
72 static void print_counter(struct perf_evsel *counter, char *prefix);
317 * Does the counter have nsecs as a unit?
356 static void update_shadow_stats(struct perf_evsel *counter, u64 *count, update_shadow_stats() argument
359 if (perf_evsel__match(counter, SOFTWARE, SW_TASK_CLOCK)) update_shadow_stats()
361 else if (perf_evsel__match(counter, HARDWARE, HW_CPU_CYCLES)) update_shadow_stats()
364 perf_evsel__cmp(counter, nth_evsel(T_CYCLES_IN_TX))) update_shadow_stats()
367 perf_evsel__cmp(counter, nth_evsel(T_TRANSACTION_START))) update_shadow_stats()
370 perf_evsel__cmp(counter, nth_evsel(T_ELISION_START))) update_shadow_stats()
372 else if (perf_evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) update_shadow_stats()
374 else if (perf_evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND)) update_shadow_stats()
376 else if (perf_evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS)) update_shadow_stats()
378 else if (perf_evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES)) update_shadow_stats()
380 else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_L1D)) update_shadow_stats()
382 else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_L1I)) update_shadow_stats()
384 else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_LL)) update_shadow_stats()
386 else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_DTLB)) update_shadow_stats()
388 else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_ITLB)) update_shadow_stats()
392 static void zero_per_pkg(struct perf_evsel *counter) zero_per_pkg() argument
394 if (counter->per_pkg_mask) zero_per_pkg()
395 memset(counter->per_pkg_mask, 0, MAX_NR_CPUS); zero_per_pkg()
398 static int check_per_pkg(struct perf_evsel *counter, int cpu, bool *skip) check_per_pkg() argument
400 unsigned long *mask = counter->per_pkg_mask; check_per_pkg()
401 struct cpu_map *cpus = perf_evsel__cpus(counter); check_per_pkg()
406 if (!counter->per_pkg) check_per_pkg()
417 counter->per_pkg_mask = mask; check_per_pkg()
436 pr_err("failed to read per-pkg counter\n"); read_cb()
467 static int read_counter(struct perf_evsel *counter);
470 * Read out the results of a single counter:
473 static int read_counter_aggr(struct perf_evsel *counter) read_counter_aggr() argument
475 struct perf_counts_values *aggr = &counter->counts->aggr; read_counter_aggr()
476 struct perf_stat *ps = counter->priv; read_counter_aggr()
477 u64 *count = counter->counts->aggr.values; read_counter_aggr()
482 if (read_counter(counter)) read_counter_aggr()
485 if (!counter->snapshot) read_counter_aggr()
486 perf_evsel__compute_deltas(counter, -1, aggr); read_counter_aggr()
487 perf_counts_values__scale(aggr, scale, &counter->counts->scaled); read_counter_aggr()
494 perf_evsel__name(counter), count[0], count[1], count[2]); read_counter_aggr()
500 update_shadow_stats(counter, count, 0); read_counter_aggr()
506 * Read out the results of a single counter:
509 static int read_counter(struct perf_evsel *counter) read_counter() argument
512 int ncpus = perf_evsel__nr_cpus(counter); read_counter()
515 if (!counter->supported) read_counter()
518 if (counter->system_wide) read_counter()
521 if (counter->per_pkg) read_counter()
522 zero_per_pkg(counter); read_counter()
526 if (perf_evsel__read_cb(counter, cpu, thread, read_cb)) read_counter()
537 struct perf_evsel *counter; print_interval() local
543 evlist__for_each(evsel_list, counter) { evlist__for_each()
544 ps = counter->priv; evlist__for_each()
546 read_counter_aggr(counter); evlist__for_each()
549 evlist__for_each(evsel_list, counter) { evlist__for_each()
550 ps = counter->priv; evlist__for_each()
552 read_counter(counter); evlist__for_each()
586 evlist__for_each(evsel_list, counter)
587 print_counter(counter, prefix);
591 evlist__for_each(evsel_list, counter)
592 print_counter_aggr(counter, prefix);
600 struct perf_evsel *counter; handle_initial_delay() local
607 evlist__for_each(evsel_list, counter) handle_initial_delay()
608 perf_evsel__enable(counter, ncpus, nthreads); handle_initial_delay()
629 struct perf_evsel *counter; __run_perf_stat() local
655 evlist__for_each(evsel_list, counter) { evlist__for_each()
656 if (create_perf_stat_counter(counter) < 0) { evlist__for_each()
666 perf_evsel__name(counter)); evlist__for_each()
667 counter->supported = false; evlist__for_each()
671 perf_evsel__open_strerror(counter, &target, evlist__for_each()
680 counter->supported = true; evlist__for_each()
682 l = strlen(counter->unit); evlist__for_each()
687 if (perf_evlist__apply_filters(evsel_list, &counter)) {
689 counter->filter, perf_evsel__name(counter), errno,
734 evlist__for_each(evsel_list, counter) { evlist__for_each()
735 read_counter_aggr(counter); evlist__for_each()
736 perf_evsel__close_fd(counter, perf_evsel__nr_cpus(counter), evlist__for_each()
740 evlist__for_each(evsel_list, counter) { evlist__for_each()
741 read_counter(counter); evlist__for_each()
742 perf_evsel__close_fd(counter, perf_evsel__nr_cpus(counter), 1); evlist__for_each()
1229 struct perf_evsel *counter; print_aggr() local
1239 evlist__for_each(evsel_list, counter) { evlist__for_each()
1242 for (cpu = 0; cpu < perf_evsel__nr_cpus(counter); cpu++) { evlist__for_each()
1243 s2 = aggr_get_id(perf_evsel__cpus(counter), cpu); evlist__for_each()
1246 val += counter->counts->cpu[cpu].val; evlist__for_each()
1247 ena += counter->counts->cpu[cpu].ena; evlist__for_each()
1248 run += counter->counts->cpu[cpu].run; evlist__for_each()
1255 aggr_printout(counter, id, nr); evlist__for_each()
1259 counter->supported ? CNTR_NOT_COUNTED : CNTR_NOT_SUPPORTED, evlist__for_each()
1264 counter->unit, csv_sep); evlist__for_each()
1268 perf_evsel__name(counter)); evlist__for_each()
1270 if (counter->cgrp) evlist__for_each()
1272 csv_sep, counter->cgrp->name); evlist__for_each()
1278 uval = val * counter->scale; evlist__for_each()
1280 if (nsec_counter(counter)) evlist__for_each()
1281 nsec_printout(id, nr, counter, uval); evlist__for_each()
1283 abs_printout(id, nr, counter, uval); evlist__for_each()
1286 print_noise(counter, 1.0); evlist__for_each()
1295 * Print out the results of a single counter:
1298 static void print_counter_aggr(struct perf_evsel *counter, char *prefix) print_counter_aggr() argument
1300 struct perf_stat *ps = counter->priv; print_counter_aggr()
1302 int scaled = counter->counts->scaled; print_counter_aggr()
1312 if (scaled == -1 || !counter->supported) { print_counter_aggr()
1315 counter->supported ? CNTR_NOT_COUNTED : CNTR_NOT_SUPPORTED, print_counter_aggr()
1319 counter->unit, csv_sep); print_counter_aggr()
1322 perf_evsel__name(counter)); print_counter_aggr()
1324 if (counter->cgrp) print_counter_aggr()
1325 fprintf(output, "%s%s", csv_sep, counter->cgrp->name); print_counter_aggr()
1332 uval = avg * counter->scale; print_counter_aggr()
1334 if (nsec_counter(counter)) print_counter_aggr()
1335 nsec_printout(-1, 0, counter, uval); print_counter_aggr()
1337 abs_printout(-1, 0, counter, uval); print_counter_aggr()
1339 print_noise(counter, avg); print_counter_aggr()
1346 * Print out the results of a single counter:
1349 static void print_counter(struct perf_evsel *counter, char *prefix) print_counter() argument
1355 for (cpu = 0; cpu < perf_evsel__nr_cpus(counter); cpu++) { print_counter()
1356 val = counter->counts->cpu[cpu].val; print_counter()
1357 ena = counter->counts->cpu[cpu].ena; print_counter()
1358 run = counter->counts->cpu[cpu].run; print_counter()
1366 perf_evsel__cpus(counter)->map[cpu], csv_sep, print_counter()
1368 counter->supported ? CNTR_NOT_COUNTED : CNTR_NOT_SUPPORTED, print_counter()
1373 counter->unit, csv_sep); print_counter()
1377 perf_evsel__name(counter)); print_counter()
1379 if (counter->cgrp) print_counter()
1381 csv_sep, counter->cgrp->name); print_counter()
1388 uval = val * counter->scale; print_counter()
1390 if (nsec_counter(counter)) print_counter()
1391 nsec_printout(cpu, 0, counter, uval); print_counter()
1393 abs_printout(cpu, 0, counter, uval); print_counter()
1396 print_noise(counter, 1.0); print_counter()
1405 struct perf_evsel *counter; print_stat() local
1412 fprintf(output, " Performance counter stats for "); print_stat()
1438 evlist__for_each(evsel_list, counter) print_stat()
1439 print_counter_aggr(counter, NULL); print_stat()
1442 evlist__for_each(evsel_list, counter) print_stat()
1443 print_counter(counter, NULL); print_stat()
1732 "put the counters into a counter group"), cmd_stat()
1735 "be more verbose (show counter open errors, etc)"), cmd_stat()
/linux-4.1.27/arch/x86/include/asm/
H A Datomic64_64.h21 return ACCESS_ONCE((v)->counter); atomic64_read()
33 v->counter = i; atomic64_set()
46 : "=m" (v->counter) atomic64_add()
47 : "er" (i), "m" (v->counter)); atomic64_add()
60 : "=m" (v->counter) atomic64_sub()
61 : "er" (i), "m" (v->counter)); atomic64_sub()
75 GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, "er", i, "%0", "e"); atomic64_sub_and_test()
87 : "=m" (v->counter) atomic64_inc()
88 : "m" (v->counter)); atomic64_inc()
100 : "=m" (v->counter) atomic64_dec()
101 : "m" (v->counter)); atomic64_dec()
114 GEN_UNARY_RMWcc(LOCK_PREFIX "decq", v->counter, "%0", "e"); atomic64_dec_and_test()
127 GEN_UNARY_RMWcc(LOCK_PREFIX "incq", v->counter, "%0", "e"); atomic64_inc_and_test()
141 GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, "er", i, "%0", "s"); atomic64_add_negative()
153 return i + xadd(&v->counter, i); atomic64_add_return()
166 return cmpxchg(&v->counter, old, new); atomic64_cmpxchg()
171 return xchg(&v->counter, new); atomic64_xchg()
H A Dlocal.h21 : "+m" (l->a.counter)); local_inc()
27 : "+m" (l->a.counter)); local_dec()
33 : "+m" (l->a.counter) local_add()
40 : "+m" (l->a.counter) local_sub()
55 GEN_BINARY_RMWcc(_ASM_SUB, l->a.counter, "er", i, "%0", "e"); local_sub_and_test()
68 GEN_UNARY_RMWcc(_ASM_DEC, l->a.counter, "%0", "e"); local_dec_and_test()
81 GEN_UNARY_RMWcc(_ASM_INC, l->a.counter, "%0", "e"); local_inc_and_test()
95 GEN_BINARY_RMWcc(_ASM_ADD, l->a.counter, "er", i, "%0", "s"); local_add_negative()
109 : "+r" (i), "+m" (l->a.counter) local_add_return()
123 (cmpxchg_local(&((l)->a.counter), (o), (n)))
125 #define local_xchg(l, n) (xchg(&((l)->a.counter), (n)))
H A Datomic.h27 return ACCESS_ONCE((v)->counter); atomic_read()
39 v->counter = i; atomic_set()
52 : "+m" (v->counter) atomic_add()
66 : "+m" (v->counter) atomic_sub()
81 GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, "er", i, "%0", "e"); atomic_sub_and_test()
93 : "+m" (v->counter)); atomic_inc()
105 : "+m" (v->counter)); atomic_dec()
118 GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, "%0", "e"); atomic_dec_and_test()
131 GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, "%0", "e"); atomic_inc_and_test()
145 GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, "er", i, "%0", "s"); atomic_add_negative()
157 return i + xadd(&v->counter, i); atomic_add_return()
177 return cmpxchg(&v->counter, old, new); atomic_cmpxchg()
182 return xchg(&v->counter, new); atomic_xchg()
/linux-4.1.27/net/dccp/ccids/lib/
H A Dloss_interval.c25 /* the `counter' index always points at the next entry to be populated */ tfrc_lh_peek()
28 return lh->counter ? lh->ring[LIH_INDEX(lh->counter - 1)] : NULL; tfrc_lh_peek()
34 BUG_ON(i >= lh->counter); tfrc_lh_get_interval()
35 return lh->ring[LIH_INDEX(lh->counter - i - 1)]->li_length; tfrc_lh_get_interval()
43 if (lh->ring[LIH_INDEX(lh->counter)] == NULL) tfrc_lh_demand_next()
44 lh->ring[LIH_INDEX(lh->counter)] = kmem_cache_alloc(tfrc_lh_slab, tfrc_lh_demand_next()
46 return lh->ring[LIH_INDEX(lh->counter)]; tfrc_lh_demand_next()
54 for (lh->counter = 0; lh->counter < LIH_SIZE; lh->counter++) tfrc_lh_cleanup()
55 if (lh->ring[LIH_INDEX(lh->counter)] != NULL) { tfrc_lh_cleanup()
57 lh->ring[LIH_INDEX(lh->counter)]); tfrc_lh_cleanup()
58 lh->ring[LIH_INDEX(lh->counter)] = NULL; tfrc_lh_cleanup()
157 if (++lh->counter == 1) tfrc_lh_interval_add()
163 if (lh->counter > (2*LIH_SIZE)) tfrc_lh_interval_add()
164 lh->counter -= LIH_SIZE; tfrc_lh_interval_add()
H A Dloss_interval.h42 * @counter: Current count of entries (can be more than %LIH_SIZE)
47 u8 counter; member in struct:tfrc_loss_hist
58 return lh->counter > 0; tfrc_lh_is_initialised()
63 return min(lh->counter, (u8)LIH_SIZE); tfrc_lh_length()
/linux-4.1.27/arch/x86/kernel/
H A Dtrace_clock.c9 * trace_clock_x86_tsc(): A clock that is just the cycle counter.
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-ps2.h17 * counter reg PS2_CNT
/linux-4.1.27/arch/parisc/include/asm/
H A Dspinlock_types.h16 volatile int counter; member in struct:__anon2209
H A Dspinlock.h64 * In the PA-RISC implementation, we have a spinlock and a counter.
65 * Readers use the lock to serialise their access to the counter (which
78 rw->counter++; arch_read_lock()
90 rw->counter--; arch_read_unlock()
103 rw->counter++; arch_read_trylock()
111 if (rw->counter < 0) arch_read_trylock()
115 while (arch_spin_is_locked(&rw->lock) && rw->counter >= 0) arch_read_trylock()
130 if (rw->counter != 0) { arch_write_lock()
134 while (rw->counter != 0) arch_write_lock()
140 rw->counter = -1; /* mark as write-locked */ arch_write_lock()
147 rw->counter = 0; arch_write_unlock()
160 if (rw->counter == 0) { arch_write_trylock()
161 rw->counter = -1; arch_write_trylock()
179 return rw->counter >= 0; arch_read_can_lock()
188 return !rw->counter; arch_write_can_lock()
H A Datomic.h63 v->counter = i; atomic_set()
70 return ACCESS_ONCE((v)->counter); atomic_read()
74 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
75 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
107 v->counter c_op i; \
118 ret = (v->counter c_op i); \
167 v->counter c_op i; \
178 ret = (v->counter c_op i); \
199 v->counter = i; atomic64_set()
207 return ACCESS_ONCE((v)->counter); atomic64_read()
224 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
225 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
/linux-4.1.27/arch/arm/kernel/
H A Dperf_event_v6.c2 * ARMv6 Performance counter handling code.
6 * ARMv6 has 2 configurable performance counters and a single cycle counter.
15 * the event bus. The procedure for disabling a configurable counter is:
16 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
17 * effectively stops the counter from counting.
18 * - disable the counter's interrupt generation (each counter has it's
20 * Once stopped, the counter value can be written as 0 to reset.
22 * To enable a counter:
23 * - enable the counter's interrupt generation.
26 * Note: the dedicated cycle counter only counts cycles and can't be
28 * cycle counter, we have to just disable the interrupt reporting and start
29 * ignoring that counter. When re-enabling, we have to reset the value and
98 * can use a raw counter.
161 * can use a raw counter.
211 enum armv6_counters counter) armv6_pmcr_counter_has_overflowed()
215 if (ARMV6_CYCLE_COUNTER == counter) armv6_pmcr_counter_has_overflowed()
217 else if (ARMV6_COUNTER0 == counter) armv6_pmcr_counter_has_overflowed()
219 else if (ARMV6_COUNTER1 == counter) armv6_pmcr_counter_has_overflowed()
222 WARN_ONCE(1, "invalid counter number (%d)\n", counter); armv6_pmcr_counter_has_overflowed()
230 int counter = hwc->idx; armv6pmu_read_counter() local
233 if (ARMV6_CYCLE_COUNTER == counter) armv6pmu_read_counter()
235 else if (ARMV6_COUNTER0 == counter) armv6pmu_read_counter()
237 else if (ARMV6_COUNTER1 == counter) armv6pmu_read_counter()
240 WARN_ONCE(1, "invalid counter number (%d)\n", counter); armv6pmu_read_counter()
248 int counter = hwc->idx; armv6pmu_write_counter() local
250 if (ARMV6_CYCLE_COUNTER == counter) armv6pmu_write_counter()
252 else if (ARMV6_COUNTER0 == counter) armv6pmu_write_counter()
254 else if (ARMV6_COUNTER1 == counter) armv6pmu_write_counter()
257 WARN_ONCE(1, "invalid counter number (%d)\n", counter); armv6pmu_write_counter()
280 WARN_ONCE(1, "invalid counter number (%d)\n", idx); armv6pmu_enable_event()
285 * Mask out the current event and set the counter to count the event armv6pmu_enable_event()
329 * each counter has overflowed before we process it. armv6pmu_handle_irq()
385 /* Always place a cycle counter into the cycle counter. */ armv6pmu_get_event_idx()
393 * For anything other than a cycle counter, try and use armv6pmu_get_event_idx()
425 WARN_ONCE(1, "invalid counter number (%d)\n", idx); armv6pmu_disable_event()
430 * Mask out the current event and set the counter to count the number armv6pmu_disable_event()
457 WARN_ONCE(1, "invalid counter number (%d)\n", idx); armv6mpcore_pmu_disable_event()
210 armv6_pmcr_counter_has_overflowed(unsigned long pmcr, enum armv6_counters counter) armv6_pmcr_counter_has_overflowed() argument
H A Dperf_event_xscale.c2 * ARMv5 [xscale] Performance counter handling code.
9 * - xscale1pmu: 2 event counters and a cycle counter
10 * - xscale2pmu: 4 event counters and a cycle counter
114 enum xscale_counters counter) xscale1_pmnc_counter_has_overflowed()
118 switch (counter) { xscale1_pmnc_counter_has_overflowed()
129 WARN_ONCE(1, "invalid counter number (%d)\n", counter); xscale1_pmnc_counter_has_overflowed()
220 WARN_ONCE(1, "invalid counter number (%d)\n", idx); xscale1pmu_enable_event()
254 WARN_ONCE(1, "invalid counter number (%d)\n", idx); xscale1pmu_disable_event()
314 int counter = hwc->idx; xscale1pmu_read_counter() local
317 switch (counter) { xscale1pmu_read_counter()
335 int counter = hwc->idx; xscale1pmu_write_counter() local
337 switch (counter) { xscale1pmu_write_counter()
455 enum xscale_counters counter) xscale2_pmnc_counter_has_overflowed()
459 switch (counter) { xscale2_pmnc_counter_has_overflowed()
476 WARN_ONCE(1, "invalid counter number (%d)\n", counter); xscale2_pmnc_counter_has_overflowed()
573 WARN_ONCE(1, "invalid counter number (%d)\n", idx); xscale2pmu_enable_event()
624 WARN_ONCE(1, "invalid counter number (%d)\n", idx); xscale2pmu_disable_event()
678 int counter = hwc->idx; xscale2pmu_read_counter() local
681 switch (counter) { xscale2pmu_read_counter()
705 int counter = hwc->idx; xscale2pmu_write_counter() local
707 switch (counter) { xscale2pmu_write_counter()
113 xscale1_pmnc_counter_has_overflowed(unsigned long pmnc, enum xscale_counters counter) xscale1_pmnc_counter_has_overflowed() argument
454 xscale2_pmnc_counter_has_overflowed(unsigned long of_flags, enum xscale_counters counter) xscale2_pmnc_counter_has_overflowed() argument
H A Dperf_event_v7.c11 * a single cycle counter.
13 * a single cycle counter.
16 * counter and all 4 performance counters together can be reset separately.
530 * DTLB refills misses a raw counter must be used.
570 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
629 u32 counter = ARMV7_IDX_TO_COUNTER(idx); armv7_pmnc_select_counter() local
630 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); armv7_pmnc_select_counter()
642 pr_err("CPU%u reading wrong counter %d\n", armv7pmu_read_counter()
661 pr_err("CPU%u writing wrong counter %d\n", armv7pmu_write_counter()
680 u32 counter = ARMV7_IDX_TO_COUNTER(idx); armv7_pmnc_enable_counter() local
681 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); armv7_pmnc_enable_counter()
686 u32 counter = ARMV7_IDX_TO_COUNTER(idx); armv7_pmnc_disable_counter() local
687 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); armv7_pmnc_disable_counter()
692 u32 counter = ARMV7_IDX_TO_COUNTER(idx); armv7_pmnc_enable_intens() local
693 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); armv7_pmnc_enable_intens()
698 u32 counter = ARMV7_IDX_TO_COUNTER(idx); armv7_pmnc_disable_intens() local
699 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); armv7_pmnc_disable_intens()
702 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); armv7_pmnc_disable_intens()
768 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", armv7pmu_enable_event()
774 * Enable counter and interrupt, and set the counter to count armv7pmu_enable_event()
780 * Disable counter armv7pmu_enable_event()
786 * We only need to set the event for the cycle counter if we armv7pmu_enable_event()
793 * Enable interrupt for this counter armv7pmu_enable_event()
798 * Enable counter armv7pmu_enable_event()
814 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", armv7pmu_disable_event()
820 * Disable counter and interrupt armv7pmu_disable_event()
825 * Disable counter armv7pmu_disable_event()
830 * Disable interrupt for this counter armv7pmu_disable_event()
858 * Handle the counter(s) overflow(s) armv7pmu_handle_irq()
872 * each counter has overflowed before we process it. armv7pmu_handle_irq()
929 /* Always place a cycle counter into the cycle counter. */ armv7pmu_get_event_idx()
938 * For anything other than a cycle counter, try and use armv7pmu_get_event_idx()
981 /* The counter and interrupt enable registers are unknown at reset. */ armv7pmu_reset()
1066 /* Add the CPU cycles counter and return */ armv7_read_num_pmnc_events()
1349 /* Disable counter and interrupt */ krait_pmu_disable_event()
1352 /* Disable counter */ krait_pmu_disable_event()
1361 /* Disable interrupt for this counter */ krait_pmu_disable_event()
1376 * Enable counter and interrupt, and set the counter to count krait_pmu_enable_event()
1381 /* Disable counter */ krait_pmu_enable_event()
1386 * We set the event for the cycle counter because we krait_pmu_enable_event()
1394 /* Enable interrupt for this counter */ krait_pmu_enable_event()
1397 /* Enable counter */ krait_pmu_enable_event()
1682 /* Disable counter and interrupt */ scorpion_pmu_disable_event()
1685 /* Disable counter */ scorpion_pmu_disable_event()
1694 /* Disable interrupt for this counter */ scorpion_pmu_disable_event()
1709 * Enable counter and interrupt, and set the counter to count scorpion_pmu_enable_event()
1714 /* Disable counter */ scorpion_pmu_enable_event()
1719 * We don't set the event for the cycle counter because we scorpion_pmu_enable_event()
1727 /* Enable interrupt for this counter */ scorpion_pmu_enable_event()
1730 /* Enable counter */ scorpion_pmu_enable_event()
/linux-4.1.27/arch/s390/include/asm/
H A Datomic.h41 : "=d" (old_val), "+Q" ((ptr)->counter) \
65 : "=&d" (old_val), "=&d" (new_val), "+Q" ((ptr)->counter)\
79 : "=d" (c) : "Q" (v->counter)); atomic_read()
87 : "=Q" (v->counter) : "d" (i)); atomic_set()
101 : "+Q" (v->counter) atomic_add()
131 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
137 : "+d" (old), "+Q" (v->counter) atomic_cmpxchg()
181 : "=d" (old_val), "+Q" ((ptr)->counter) \
205 : "=&d" (old_val), "=&d" (new_val), "+Q" ((ptr)->counter)\
219 : "=d" (c) : "Q" (v->counter)); atomic64_read()
227 : "=Q" (v->counter) : "d" (i)); atomic64_set()
241 : "+Q" (v->counter) atomic64_add()
260 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
267 : "+d" (old), "+Q" (v->counter) atomic64_cmpxchg()
H A Dcpu_mf.h23 #define CPU_MF_INT_CF_CACA (1 << 7) /* counter auth. change alert */
24 #define CPU_MF_INT_CF_LCDA (1 << 6) /* loss of counter data alert */
149 /* Query counter information */ qctri()
163 /* Load CPU-counter-set controls */ lcctl()
176 /* Extract CPU counter */ ecctr()
192 /* Store CPU counter multiple for the MT utilization counter set */ stcctm5()
/linux-4.1.27/arch/frv/include/asm/
H A Datomic.h34 #define atomic_read(v) ACCESS_ONCE((v)->counter)
35 #define atomic_set(v, i) (((v)->counter) = (i))
51 : "+U"(v->counter), "=&r"(val) atomic_add_return()
72 : "+U"(v->counter), "=&r"(val) atomic_sub_return()
123 volatile long long counter; member in struct:__anon1383
130 long long counter; atomic64_read() local
133 : "=e"(counter) atomic64_read()
134 : "m"(v->counter)); atomic64_read()
135 return counter; atomic64_read()
141 : "=m"(v->counter) atomic64_set()
179 #define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new))
180 #define atomic_xchg(v, new) (xchg(&(v)->counter, new))
181 #define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter))
182 #define atomic64_xchg(v, new) (__xchg_64(new, &(v)->counter))
/linux-4.1.27/arch/arm64/include/asm/
H A Datomic.h38 #define atomic_read(v) ACCESS_ONCE((v)->counter)
39 #define atomic_set(v,i) (((v)->counter) = (i))
58 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
73 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
106 : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter) atomic_cmpxchg()
114 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
142 #define atomic64_read(v) ACCESS_ONCE((v)->counter)
143 #define atomic64_set(v,i) (((v)->counter) = (i))
156 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
171 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
204 : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter) atomic64_cmpxchg()
212 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
227 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) atomic64_dec_if_positive()
/linux-4.1.27/arch/avr32/oprofile/
H A Dop_model_avr32.c40 static struct avr32_perf_counter counter[NR_counter] = { variable in typeref:struct:avr32_perf_counter
55 /* Reset all counter and disable/clear all interrupts */ avr32_perf_counter_reset()
111 &counter[i].enabled); avr32_perf_counter_create_files()
113 &counter[i].event); avr32_perf_counter_create_files()
115 &counter[i].count); avr32_perf_counter_create_files()
119 &counter[i].kernel); avr32_perf_counter_create_files()
121 &counter[i].user); avr32_perf_counter_create_files()
123 &counter[i].unit_mask); avr32_perf_counter_create_files()
140 "oprofile: setup: perf counter already enabled\n"); avr32_perf_counter_setup()
146 "oprofile", counter); avr32_perf_counter_setup()
154 ctr = &counter[i]; avr32_perf_counter_setup()
158 pr_debug("enabling counter %d...\n", i); avr32_perf_counter_setup()
190 free_irq(AVR32_PERFCTR_IRQ_GROUP, counter); avr32_perf_counter_shutdown()
/linux-4.1.27/arch/mn10300/include/asm/
H A Datomic.h1 /* MN10300 Atomic counter operations
37 #define atomic_read(v) (ACCESS_ONCE((v)->counter))
46 #define atomic_set(v, i) (((v)->counter) = (i))
62 : "=&r"(status), "=&r"(retval), "=m"(v->counter) \
63 : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
81 : "=&r"(status), "=&r"(retval), "=m"(v->counter) \
82 : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
127 #define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
128 #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
H A Dreset-regs.h23 #define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */
32 #define WDCTR_WDRST 0x40 /* binary counter reset */
H A Dtimer-regs.h95 #define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */
96 #define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */
97 #define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */
98 #define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */
99 #define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */
295 #define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */
296 #define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */
297 #define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */
298 #define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */
299 #define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */
300 #define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */
301 #define TM89BC __SYSREG(0xd40030a8, u32) /* timer 8:9 binary counter */
302 #define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */
303 #define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */
305 #define TM12BC __SYSREG(0xd40031a0, u16) /* timer 12 binary counter */
306 #define TM13BC __SYSREG(0xd40031a2, u16) /* timer 13 binary counter */
307 #define TM14BC __SYSREG(0xd40031a4, u16) /* timer 14 binary counter */
308 #define TM15BC __SYSREG(0xd40031a6, u16) /* timer 15 binary counter */
412 #define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */
/linux-4.1.27/arch/arc/include/asm/
H A Datomic.h20 #define atomic_read(v) ((v)->counter)
24 #define atomic_set(v, i) (((v)->counter) = (i))
37 : "r"(&v->counter), "ir"(i) \
58 : "r"(&v->counter), "ir"(i) \
71 #define atomic_set(v, i) (((v)->counter) = (i))
89 v->counter = i; atomic_set()
106 v->counter c_op i; \
120 temp = v->counter; \
122 v->counter = temp; \
H A Dspinlock_types.h28 volatile unsigned int counter; member in struct:__anon138
33 #define __ARCH_RW_LOCK_UNLOCKED { .counter = __ARCH_RW_LOCK_UNLOCKED__ }
H A Dspinlock.h94 * The spinlock itself is contained in @counter and access to it is
101 #define arch_read_can_lock(x) ((x)->counter > 0)
104 #define arch_write_can_lock(x) ((x)->counter == __ARCH_RW_LOCK_UNLOCKED__)
117 if (rw->counter > 0) { arch_read_trylock()
118 rw->counter--; arch_read_trylock()
141 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { arch_write_trylock()
142 rw->counter = 0; arch_write_trylock()
165 rw->counter++; arch_read_unlock()
172 rw->counter = __ARCH_RW_LOCK_UNLOCKED__; arch_write_unlock()
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A DdefBF609.h248 #define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
249 #define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
250 #define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
251 #define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
252 #define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
253 #define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
254 #define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
255 #define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
256 #define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
257 #define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
258 #define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
259 #define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
260 #define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
261 #define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
262 #define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
263 #define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
264 #define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
265 #define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
266 #define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
267 #define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
268 #define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
269 #define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
270 #define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
271 #define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
272 #define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
273 #define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
274 #define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
275 #define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
276 #define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
277 #define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
278 #define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
279 #define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
280 #define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
281 #define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
/linux-4.1.27/arch/sparc/lib/
H A Datomic32.c37 ret = (v->counter cop i); \
54 ret = v->counter; atomic_xchg()
55 v->counter = new; atomic_xchg()
67 ret = v->counter; atomic_cmpxchg()
69 v->counter = new; atomic_cmpxchg()
82 ret = v->counter; __atomic_add_unless()
84 v->counter += a; __atomic_add_unless()
96 v->counter = i; atomic_set()
/linux-4.1.27/arch/s390/kernel/vdso32/
H A Dclock_gettime.S35 1: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
59 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
78 9: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
83 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
88 10: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
93 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
98 11: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
122 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
/linux-4.1.27/drivers/net/ethernet/apple/
H A Dbmac.h56 # define RxFrameCntExp 0x00000002 /* Receive frame counter expired */
57 # define RxAlignCntExp 0x00000004 /* Align-error counter expired */
58 # define RxCRCCntExp 0x00000008 /* CRC-error counter expired */
59 # define RxLenCntExp 0x00000010 /* Length-error counter expired */
61 # define RxCodeViolation 0x00000040 /* Code-violation counter expired */
66 # define TxNormalCollExp 0x00000800 /* Normal-collision counter expired */
67 # define TxExcessCollExp 0x00001000 /* Excess-collision counter expired */
68 # define TxLateCollExp 0x00002000 /* Late-collision counter expired */
69 # define TxNetworkCollExp 0x00004000 /* First-collision counter expired */
120 #define NCCNT 0x500 /* Transmit normal-collision counter */
121 #define NTCNT 0x510 /* Transmit first-collision counter */
122 #define EXCNT 0x520 /* Transmit excess-collision counter */
123 #define LTCNT 0x530 /* Transmit late-collision counter */
146 #define FRCNT 0x690 /* receive frame counter */
147 #define LECNT 0x6a0 /* Receive excess length error counter */
148 #define AECNT 0x6b0 /* Receive misaligned error counter */
149 #define FECNT 0x6c0 /* Receive CRC error counter */
/linux-4.1.27/arch/s390/kernel/
H A Dperf_cpum_cf.c25 /* CPU-measurement counter facility supports these CPU counter sets:
26 * For CPU counter sets:
27 * Basic counter set: 0-31
28 * Problem-state counter set: 32-63
29 * Crypto-activity counter set: 64-127
30 * Extented counter set: 128-159
33 /* CPU counter sets */
39 /* Maximum number of counter sets */
130 /* check required version for counter sets */ validate_ctr_version()
160 /* check authorization for cpu counter sets */ validate_ctr_auth()
171 * Enable and activate the CPU-counter sets according
194 * Disable and enable (inactive) the CPU-counter sets according
223 /* CPU-measurement alerts for the counter facility */ cpumf_measurement_alert()
240 /* counter authorization change alert */ cpumf_measurement_alert()
244 /* loss of counter data alert */ cpumf_measurement_alert()
267 /* Disable CPU counter sets */ setup_pmc_cpu()
370 /* Use the hardware perf event structure to store the counter number __hw_perf_event_init()
371 * in 'config' member and the counter set to which the counter belongs __hw_perf_event_init()
372 * in the 'config_base'. The counter set (config_base) is then used __hw_perf_event_init()
378 /* Validate the counter that is assigned to this event. __hw_perf_event_init()
379 * Because the counter facility can use numerous counters at the __hw_perf_event_init()
387 /* Initialize for using the CPU-measurement counter facility */ __hw_perf_event_init()
398 /* Finally, validate version and authorization of the counter set */ __hw_perf_event_init()
437 /* The counter is not (yet) available. This hw_perf_event_reset()
438 * might happen if the counter set to which hw_perf_event_reset()
439 * this counter belongs is in the disabled hw_perf_event_reset()
492 /* (Re-)enable and activate the counter set */ cpumf_pmu_start()
496 /* The counter set to which this counter belongs can be already active. cpumf_pmu_start()
498 * needs to be synchronized. At this point, the counter set can be in cpumf_pmu_start()
503 /* increment refcount for this counter set */ cpumf_pmu_start()
513 /* Decrement reference count for this counter set and if this cpumf_pmu_stop()
514 * is the last used counter in the set, clear activation cpumf_pmu_stop()
515 * control and set the counter set state to inactive. cpumf_pmu_stop()
532 /* Check authorization for the counter set to which this cpumf_pmu_add()
533 * counter belongs. cpumf_pmu_add()
558 /* Check if any counter in the counter set is still used. If not used, cpumf_pmu_del()
559 * change the counter set to the disabled state. This also clears the cpumf_pmu_del()
564 * cpumf_pmu_start() always has to reenable a counter set. cpumf_pmu_del()
678 /* The CPU measurement counter facility does not have overflow cpumf_pmu_init()
/linux-4.1.27/drivers/md/
H A Dbitmap.h23 * This means that the counter is actually 14 bits:
26 * | resync | resync | counter |
44 * The counter counts pending write requests, plus the on-disk bit.
45 * When the counter is '1' and the resync bits are clear, the on-disk
46 * bit can be cleared as well, thus setting the counter to 0.
47 * When we set a bit, or in the counter (to start a write), if the fields is
48 * 0, we first set the disk bit and set the counter to 1.
50 * If the counter is 0, the on-disk bit is clear and the stipe is clean
51 * Anything that dirties the stipe pushes the counter to 2 (at least)
53 * If a periodic sweep find the counter at 2, it is decremented to 1.
54 * If the sweep find the counter at 1, the on-disk bit is cleared and the
55 * counter goes to zero.
74 * counter #1 (16-bit) counter #2 (16-bit)
124 __le64 events; /* 24 event counter for the bitmap (1)*/
125 __le64 events_cleared;/*32 event counter when last bit cleared (2) */
139 * (1) This event counter is updated before the eventcounter in the md superblock
140 * When a bitmap is loaded, it is only accepted if this event counter is equal
141 * to, or one greater than, the event counter in the superblock.
142 * (2) This event counter is updated when the other one is *if*and*only*if* the
166 * If any counter in this page is '1' or '2' - and so could be
/linux-4.1.27/arch/sh/boards/mach-dreamcast/
H A Drtc.c22 /* The AICA RTC is represented by a 32-bit seconds counter stored in 2 16-bit
31 * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch.
47 /* Can't get nanoseconds with just a seconds counter. */ aica_rtc_gettimeofday()
55 * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter.
/linux-4.1.27/arch/cris/include/asm/
H A Dtimex.h13 * We don't have a cycle-counter.. but we do not support SMP anyway where this is
/linux-4.1.27/arch/m32r/include/asm/
H A Dtimex.h15 * Standard way to access the cycle counter.
H A Dlocal.h27 typedef struct { volatile int counter; } local_t; member in struct:__anon1747
37 #define local_read(l) ((l)->counter)
46 #define local_set(l, i) (((l)->counter) = (i))
68 : "r" (&l->counter), "r" (i) local_add_return()
99 : "r" (&l->counter), "r" (i) local_sub_return()
158 : "r" (&l->counter) local_inc_return()
188 : "r" (&l->counter) local_dec_return()
246 #define local_cmpxchg(l, o, n) (cmpxchg_local(&((l)->counter), (o), (n)))
247 #define local_xchg(v, new) (xchg_local(&((l)->counter), new))
330 #define __local_inc(l) ((l)->a.counter++)
331 #define __local_dec(l) ((l)->a.counter++)
332 #define __local_add(i, l) ((l)->a.counter += (i))
333 #define __local_sub(i, l) ((l)->a.counter -= (i))
H A Datomic.h31 #define atomic_read(v) ACCESS_ONCE((v)->counter)
40 #define atomic_set(v,i) (((v)->counter) = (i))
62 : "r" (&v->counter), "r" (i) \
83 : "r" (&v->counter), "r" (i) \
131 : "r" (&v->counter) atomic_inc_return()
159 : "r" (&v->counter) atomic_dec_return()
215 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
216 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
/linux-4.1.27/arch/arm/include/asm/xen/
H A Devents.h21 counter), (val))
/linux-4.1.27/arch/mips/sgi-ip22/
H A Dip22-time.c37 /* Start the counter. */ dosample()
43 /* Get initial counter invariant */ dosample()
54 /* Stop the counter. */ dosample()
58 * Return the difference, this is how far the r4k counter increments dosample()
67 * Here we need to calibrate the cycle counter to at least be close.
76 * _all_ cases as long as the 8254 counter register itself works ok (as plat_time_init()
78 * we are using the onchip r4k counter/compare register to serve this plat_time_init()
/linux-4.1.27/net/netfilter/
H A Dnf_conntrack_acct.c43 struct nf_conn_counter *counter; seq_print_acct() local
49 counter = acct->counter; seq_print_acct()
51 (unsigned long long)atomic64_read(&counter[dir].packets), seq_print_acct()
52 (unsigned long long)atomic64_read(&counter[dir].bytes)); seq_print_acct()
/linux-4.1.27/drivers/net/ethernet/sun/
H A Dsunbmac.h104 #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
105 #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
106 #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
107 #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
118 #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
119 #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
120 #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
121 #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
143 #define BIGMAC_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
144 #define BIGMAC_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
145 #define BIGMAC_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
146 #define BIGMAC_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
148 #define BIGMAC_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
152 #define BIGMAC_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
153 #define BIGMAC_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
154 #define BIGMAC_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
155 #define BIGMAC_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
160 #define BIGMAC_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
161 #define BIGMAC_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
162 #define BIGMAC_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
163 #define BIGMAC_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
165 #define BIGMAC_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
169 #define BIGMAC_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
170 #define BIGMAC_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
171 #define BIGMAC_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
172 #define BIGMAC_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
H A Dsunhme.h36 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
37 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
38 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
39 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
47 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
48 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
49 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
73 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
74 #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
75 #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
76 #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
78 #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
83 #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
84 #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
85 #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
86 #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
115 #define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */
173 #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
174 #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
175 #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
176 #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
187 #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
188 #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
189 #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
190 #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
295 #define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */
/linux-4.1.27/arch/mips/kernel/
H A Dcevt-r4k.c41 * Possibly handle a performance counter interrupt.
47 * The performance counter overflow interrupt may be shared with the handle_perf_irq()
49 * performance counter has overflowed (perf_irq() == IRQ_HANDLED) handle_perf_irq()
50 * and we can't reliably determine if a counter interrupt has also handle_perf_irq()
67 * performance counter interrupt was pending, so we have to run c0_compare_interrupt()
68 * the performance counter interrupt handler anyway. c0_compare_interrupt()
74 * The same applies to performance counter interrupts. But with the c0_compare_interrupt()
94 * such as perf counter and FDC interrupts.
116 * so wait up to worst case number of cycle counter ticks for timer interrupt
H A Dcsrc-ioasic.c2 * DEC I/O ASIC's counter clocksource
62 /* An early revision of the I/O ASIC didn't have the counter. */ dec_ioasic_clocksource_init()
H A Dperf_event.c2 * Linux performance counter support for MIPS.
9 * counter access is based on the MIPS Oprofile code. And the callchain
/linux-4.1.27/arch/mips/oprofile/
H A Dop_model_loongson2.c2 * Loongson2 performance counter driver for oprofile
60 * Compute the performance counter ctrl word. loongson2_reg_setup()
108 uint64_t counter, counter1, counter2; loongson2_perfcount_handler() local
120 counter = read_c0_perfcnt(); loongson2_perfcount_handler()
121 counter1 = counter & 0xffffffff; loongson2_perfcount_handler()
122 counter2 = counter >> 32; loongson2_perfcount_handler()
H A Dop_model_mipsxx.c145 unsigned int counter[4]; member in struct:mipsxx_register_config
155 /* Compute the performance counter control word. */ mipsxx_reg_setup()
158 reg.counter[i] = 0; mipsxx_reg_setup()
173 reg.counter[i] = 0x80000000 - ctr[i].count; mipsxx_reg_setup()
189 w_c0_perfcntr3(reg.counter[3]); mipsxx_cpu_setup()
192 w_c0_perfcntr2(reg.counter[2]); mipsxx_cpu_setup()
195 w_c0_perfcntr1(reg.counter[1]); mipsxx_cpu_setup()
198 w_c0_perfcntr0(reg.counter[0]); mipsxx_cpu_setup()
246 unsigned int counter; mipsxx_perfcount_handler() local
256 counter = r_c0_perfcntr ## n(); \ mipsxx_perfcount_handler()
258 (counter & M_COUNTER_OVERFLOW)) { \ mipsxx_perfcount_handler()
260 w_c0_perfcntr ## n(reg.counter[n]); \ mipsxx_perfcount_handler()
H A Dop_impl.h15 /* Per-counter configuration as set via oprofilefs. */
/linux-4.1.27/drivers/clocksource/
H A Darm_global_timer.c57 * 1. Read the upper 32-bit timer counter register
58 * 2. Read the lower 32-bit timer counter register
59 * 3. Read the upper 32-bit timer counter register again. If the value is
61 * Otherwise the 64-bit timer counter value is correct.
65 u64 counter; gt_counter_read() local
76 counter = upper; gt_counter_read()
77 counter <<= 32; gt_counter_read()
78 counter |= lower; gt_counter_read()
79 return counter; gt_counter_read()
92 u64 counter = gt_counter_read(); gt_compare_set() local
95 counter += delta; gt_compare_set()
98 writel(lower_32_bits(counter), gt_base + GT_COMP0); gt_compare_set()
99 writel(upper_32_bits(counter), gt_base + GT_COMP1); gt_compare_set()
H A Dfsl_ftm_timer.c67 /* select and enable counter clock source */ ftm_counter_enable()
78 /* disable counter clock source */ ftm_counter_disable()
114 * The CNT register contains the FTM counter value. ftm_reset_counter()
116 * updates the counter with its initial value, CNTIN. ftm_reset_counter()
134 * a, the counter source clock is diabled. ftm_set_next_event()
138 /* Force the value of CNTIN to be loaded into the FTM counter */ ftm_set_next_event()
142 * The counter increments until the value of MOD is reached, ftm_set_next_event()
143 * at which point the counter is reloaded with the value of CNTIN. ftm_set_next_event()
144 * The TOF (the overflow flag) bit is set when the FTM counter ftm_set_next_event()
287 freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt"); ftm_clk_init()
291 freq = __ftm_clk_init(np, "ftm-src-counter-en", "ftm-src"); ftm_clk_init()
302 /* The counter register is only using the lower 16 bits, and ftm_calc_closest_round_cyc()
H A Di8253.c26 * running counter:
46 * the counter may underflow between the last point where i8253_read()
67 * 1. The timer counter underflows, but we haven't handled the i8253_read()
70 * the counter does small "jumps" upwards on some Pentium systems, i8253_read()
H A Dvf_pit_timer.c62 /* set the max load value and start the clock source counter */ pit_clocksource_init()
113 * and reload the counter value from PITLDVAL when PITCVAL reach zero, pit_timer_interrupt()
114 * and start the counter again. So software need to disable the timer pit_timer_interrupt()
115 * to stop the counter loop in ONESHOT mode. pit_timer_interrupt()
/linux-4.1.27/arch/arm64/kernel/
H A Dperf_event.c43 * The cycle counter is included in this total.
175 * Limit the maximum period to prevent the counter value armpmu_event_set_period()
235 * ARM pmu always has to update the counter, so ignore armpmu_stop()
262 * were stopped we simply disabled the IRQ source and the counter armpmu_start()
299 /* If we don't have a space for the counter then finish early. */ armpmu_add()
307 * If there is an event in the counter we are going to use then make armpmu_add()
554 * Check whether we need to exclude the counter from certain modes. __hw_perf_event_init()
571 * of the counter width. That way, the new counter value __hw_perf_event_init()
845 #define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
899 u32 counter; armv8pmu_counter_has_overflowed() local
902 pr_err("CPU%u checking wrong counter %d overflow status\n", armv8pmu_counter_has_overflowed()
905 counter = ARMV8_IDX_TO_COUNTER(idx); armv8pmu_counter_has_overflowed()
906 ret = pmnc & BIT(counter); armv8pmu_counter_has_overflowed()
914 u32 counter; armv8pmu_select_counter() local
917 pr_err("CPU%u selecting wrong PMNC counter %d\n", armv8pmu_select_counter()
922 counter = ARMV8_IDX_TO_COUNTER(idx); armv8pmu_select_counter()
923 asm volatile("msr pmselr_el0, %0" :: "r" (counter)); armv8pmu_select_counter()
934 pr_err("CPU%u reading wrong counter %d\n", armv8pmu_read_counter()
947 pr_err("CPU%u writing wrong counter %d\n", armv8pmu_write_counter()
965 u32 counter; armv8pmu_enable_counter() local
968 pr_err("CPU%u enabling wrong PMNC counter %d\n", armv8pmu_enable_counter()
973 counter = ARMV8_IDX_TO_COUNTER(idx); armv8pmu_enable_counter()
974 asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter))); armv8pmu_enable_counter()
980 u32 counter; armv8pmu_disable_counter() local
983 pr_err("CPU%u disabling wrong PMNC counter %d\n", armv8pmu_disable_counter()
988 counter = ARMV8_IDX_TO_COUNTER(idx); armv8pmu_disable_counter()
989 asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter))); armv8pmu_disable_counter()
995 u32 counter; armv8pmu_enable_intens() local
998 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", armv8pmu_enable_intens()
1003 counter = ARMV8_IDX_TO_COUNTER(idx); armv8pmu_enable_intens()
1004 asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter))); armv8pmu_enable_intens()
1010 u32 counter; armv8pmu_disable_intens() local
1013 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", armv8pmu_disable_intens()
1018 counter = ARMV8_IDX_TO_COUNTER(idx); armv8pmu_disable_intens()
1019 asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter))); armv8pmu_disable_intens()
1022 asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter))); armv8pmu_disable_intens()
1047 * Enable counter and interrupt, and set the counter to count armv8pmu_enable_event()
1053 * Disable counter armv8pmu_enable_event()
1063 * Enable interrupt for this counter armv8pmu_enable_event()
1068 * Enable counter armv8pmu_enable_event()
1081 * Disable counter and interrupt armv8pmu_disable_event()
1086 * Disable counter armv8pmu_disable_event()
1091 * Disable interrupt for this counter armv8pmu_disable_event()
1118 * Handle the counter(s) overflow(s) armv8pmu_handle_irq()
1133 * each counter has overflowed before we process it. armv8pmu_handle_irq()
1188 /* Always place a cycle counter into the cycle counter. */ armv8pmu_get_event_idx()
1197 * For anything other than a cycle counter, try and use armv8pmu_get_event_idx()
1239 /* The counter and interrupt enable registers are unknown at reset. */ armv8pmu_reset()
1274 /* Add the CPU cycles counter and return */ armv8pmu_read_num_pmnc_events()
/linux-4.1.27/arch/s390/kernel/vdso64/
H A Dclock_gettime.S36 0: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
47 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
62 3: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
67 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
72 4: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
77 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
82 5: lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
93 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
H A Dgettimeofday.S29 lg %r4,__VDSO_UPD_COUNT(%r5) /* load update counter */
38 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
/linux-4.1.27/arch/score/include/asm/
H A Dscoreregs.h47 #define TMR_M_FC 0x0800 /* free running counter mode */
48 #define TMR_M_PC 0x0c00 /* periodic counter mode */
/linux-4.1.27/arch/frv/mm/
H A Dextable.c27 * - we search for the return address (in LR) instead of the program counter search_exception_table()
37 * - we search for the return address (in LR) instead of the program counter search_exception_table()
/linux-4.1.27/drivers/infiniband/hw/ocrdma/
H A Docrdma_stats.c498 [OCRDMA_CQ_ERROR].counter)); ocrdma_driver_dbg_stats()
501 [OCRDMA_CQ_OVERRUN_ERROR].counter); ocrdma_driver_dbg_stats()
504 [OCRDMA_CQ_QPCAT_ERROR].counter); ocrdma_driver_dbg_stats()
507 [OCRDMA_QP_ACCESS_ERROR].counter); ocrdma_driver_dbg_stats()
510 [OCRDMA_QP_COMM_EST_EVENT].counter); ocrdma_driver_dbg_stats()
513 [OCRDMA_SQ_DRAINED_EVENT].counter); ocrdma_driver_dbg_stats()
516 [OCRDMA_DEVICE_FATAL_EVENT].counter); ocrdma_driver_dbg_stats()
519 [OCRDMA_SRQCAT_ERROR].counter); ocrdma_driver_dbg_stats()
522 [OCRDMA_SRQ_LIMIT_EVENT].counter); ocrdma_driver_dbg_stats()
525 [OCRDMA_QP_LAST_WQE_EVENT].counter); ocrdma_driver_dbg_stats()
529 [OCRDMA_CQE_LOC_LEN_ERR].counter); ocrdma_driver_dbg_stats()
532 [OCRDMA_CQE_LOC_QP_OP_ERR].counter); ocrdma_driver_dbg_stats()
535 [OCRDMA_CQE_LOC_EEC_OP_ERR].counter); ocrdma_driver_dbg_stats()
538 [OCRDMA_CQE_LOC_PROT_ERR].counter); ocrdma_driver_dbg_stats()
541 [OCRDMA_CQE_WR_FLUSH_ERR].counter); ocrdma_driver_dbg_stats()
544 [OCRDMA_CQE_MW_BIND_ERR].counter); ocrdma_driver_dbg_stats()
547 [OCRDMA_CQE_BAD_RESP_ERR].counter); ocrdma_driver_dbg_stats()
550 [OCRDMA_CQE_LOC_ACCESS_ERR].counter); ocrdma_driver_dbg_stats()
553 [OCRDMA_CQE_REM_INV_REQ_ERR].counter); ocrdma_driver_dbg_stats()
556 [OCRDMA_CQE_REM_ACCESS_ERR].counter); ocrdma_driver_dbg_stats()
559 [OCRDMA_CQE_REM_OP_ERR].counter); ocrdma_driver_dbg_stats()
562 [OCRDMA_CQE_RETRY_EXC_ERR].counter); ocrdma_driver_dbg_stats()
565 [OCRDMA_CQE_RNR_RETRY_EXC_ERR].counter); ocrdma_driver_dbg_stats()
568 [OCRDMA_CQE_LOC_RDD_VIOL_ERR].counter); ocrdma_driver_dbg_stats()
571 [OCRDMA_CQE_REM_INV_RD_REQ_ERR].counter); ocrdma_driver_dbg_stats()
574 [OCRDMA_CQE_REM_ABORT_ERR].counter); ocrdma_driver_dbg_stats()
577 [OCRDMA_CQE_INV_EECN_ERR].counter); ocrdma_driver_dbg_stats()
580 [OCRDMA_CQE_INV_EEC_STATE_ERR].counter); ocrdma_driver_dbg_stats()
583 [OCRDMA_CQE_FATAL_ERR].counter); ocrdma_driver_dbg_stats()
586 [OCRDMA_CQE_RESP_TIMEOUT_ERR].counter); ocrdma_driver_dbg_stats()
589 [OCRDMA_CQE_GENERAL_ERR].counter); ocrdma_driver_dbg_stats()
/linux-4.1.27/drivers/staging/vt6655/
H A Dmib.h35 // 802.11 counter
46 // Custom counter
68 // statistic counter
H A Dmib.c28 * STAvUpdateIstStatCounter - Update ISR statistic counter
29 * STAvUpdate802_11Counter - Update 802.11 mib counter
115 * Description: Update 802.11 mib counter
119 * p802_11Counter - Pointer to 802.11 mib counter
121 * dwCounter - hardware counter for 802.11 mib
/linux-4.1.27/include/uapi/linux/
H A Dmmtimer.h30 * registers are mapped) for the counter in question.
39 * Number of bits in the clock's counter
45 * Gets the current value in the counter
H A Datalk.h22 #define DDP_MAXHOPS 15 /* 4 bits of hop counter */
/linux-4.1.27/arch/m68k/include/asm/
H A Dmcftimer.h41 #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
42 #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
46 #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
H A Datomic.h20 #define atomic_read(v) ACCESS_ONCE((v)->counter)
21 #define atomic_set(v, i) (((v)->counter) = i)
65 t = (v->counter c_op i); \
120 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
121 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
H A Dintersil.h39 struct intersil_dt counter; member in struct:intersil_7170
H A Dmcfpit.h42 #define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */
45 #define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */
H A Dm68360_pram.h70 unsigned short maxc; /* Max_length counter */
107 unsigned short disfc; /* discarded frame counter */
108 unsigned short crcec; /* CRC error counter */
109 unsigned short abtsc; /* abort sequence counter */
113 unsigned short max_cnt; /* maximum length counter */
166 unsigned short idlc; /* rx idle counter (internal) */
169 unsigned short parec; /* Rx parity error counter */
170 unsigned short frmer; /* Rx framing error counter */
171 unsigned short nosec; /* Rx noise counter */
172 unsigned short brkec; /* Rx break character counter */
340 unsigned long crcec; /* CRC error counter */
341 unsigned long alec; /* alignment error counter */
342 unsigned long disfc; /* discard frame counter */
345 unsigned short ret_cnt; /* retry limit counter */
351 unsigned short dma_cnt; /* rx dma counter */
379 unsigned short tx_len; /* tx frame length counter */
384 unsigned short boff_cnt; /* back-off counter */
/linux-4.1.27/sound/drivers/pcsp/
H A Dpcsp_input.c28 /* set command for counter 2, 2 byte write */ pcspkr_do_sound()
33 /* enable counter 2 */ pcspkr_do_sound()
36 /* disable counter 2 */ pcspkr_do_sound()
/linux-4.1.27/tools/testing/selftests/powerpc/pmu/ebb/
H A Dback_to_back_ebbs_test.c16 * Test that if we overflow the counter while in the EBB handler, we take
24 * counter frozen once we've taken enough EBBs.
51 /* Do some stuff to chew some cycles and pop the counter */ ebb_callee()
/linux-4.1.27/kernel/time/
H A Dtimecounter.c35 * @tc: Pointer to time counter
37 * When the underlying cycle counter runs over, this will be handled
41 * The first call to this function for a new time counter initializes
49 /* read cycle counter: */ timecounter_read_delta()
80 * time previous to the time stored in the cycle counter.
/linux-4.1.27/tools/perf/util/
H A Dcgroup.c78 struct perf_evsel *counter; add_cgroup() local
84 evlist__for_each(evlist, counter) { evlist__for_each()
85 cgrp = counter->cgrp; evlist__for_each()
113 evlist__for_each(evlist, counter) { evlist__for_each()
124 counter->cgrp = cgrp;
/linux-4.1.27/drivers/input/joystick/
H A Dwalkera0701.c54 int counter; member in struct:walkera_dev
138 w->counter = NO_SYNC; walkera0701_irq_handler()
142 if (w->counter < NO_SYNC) { walkera0701_irq_handler()
145 w->buf[w->counter] = 8; walkera0701_irq_handler()
148 w->buf[w->counter] = 0; walkera0701_irq_handler()
150 if (w->counter == 24) { /* full frame */ walkera0701_irq_handler()
152 w->counter = NO_SYNC; walkera0701_irq_handler()
154 w->counter = 0; walkera0701_irq_handler()
160 w->buf[w->counter++] |= (pulse_time & 7); walkera0701_irq_handler()
162 w->counter = NO_SYNC; walkera0701_irq_handler()
166 w->counter = 0; walkera0701_irq_handler()
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_msgdma.c39 int counter; msgdma_reset() local
47 counter = 0; msgdma_reset()
48 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { msgdma_reset()
55 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) msgdma_reset()
69 counter = 0; msgdma_reset()
70 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { msgdma_reset()
77 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) msgdma_reset()
/linux-4.1.27/drivers/watchdog/
H A Dsirfsoc_wdt.c44 u32 counter, match; sirfsoc_wdt_gettimeleft() local
49 counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO); sirfsoc_wdt_gettimeleft()
53 time_left = match - counter; sirfsoc_wdt_gettimeleft()
60 u32 counter, timeout_ticks; sirfsoc_wdt_updatetimeout() local
70 counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO); sirfsoc_wdt_updatetimeout()
72 counter += timeout_ticks; sirfsoc_wdt_updatetimeout()
74 writel(counter, wdt_base + sirfsoc_wdt_updatetimeout()
H A Dpnx4008_wdt.c76 #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
89 /* stop counter, initiate counter reset */ pnx4008_wdt_start()
103 /*enable counter, stop when debugger active */ pnx4008_wdt_start()
114 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ pnx4008_wdt_stop()
/linux-4.1.27/arch/mips/sni/
H A Dtime.c100 /* Start the counter. */ dosample()
105 /* Get initial counter invariant */ dosample()
116 /* Stop the counter. */ dosample()
119 * Return the difference, this is how far the r4k counter increments dosample()
128 * Here we need to calibrate the cycle counter to at least be close.
137 * _all_ cases as long as the 8254 counter register itself works ok (as plat_time_init()
139 * we are using the onchip r4k counter/compare register to serve this plat_time_init()
/linux-4.1.27/drivers/net/wireless/prism54/
H A Dislpci_dev.c555 unsigned counter; islpci_reset() local
573 for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) { islpci_reset()
574 cb->driver_curr_frag[counter] = cpu_to_le32(0); islpci_reset()
575 cb->device_curr_frag[counter] = cpu_to_le32(0); islpci_reset()
579 for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) { islpci_reset()
580 isl38xx_fragment *frag = &cb->rx_data_mgmt[counter]; islpci_reset()
583 frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr); islpci_reset()
586 for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { islpci_reset()
587 cb->rx_data_low[counter].address = islpci_reset()
588 cpu_to_le32((u32) priv->pci_map_rx_address[counter]); islpci_reset()
627 int counter; islpci_alloc_memory() local
672 for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) { islpci_alloc_memory()
673 priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0); islpci_alloc_memory()
674 priv->control_block->device_curr_frag[counter] = cpu_to_le32(0); islpci_alloc_memory()
689 for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { islpci_alloc_memory()
703 priv->data_low_rx[counter] = skb; islpci_alloc_memory()
706 priv->pci_map_rx_address[counter] = islpci_alloc_memory()
710 if (!priv->pci_map_rx_address[counter]) { islpci_alloc_memory()
732 int counter; islpci_free_memory() local
751 for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) { islpci_free_memory()
752 struct islpci_membuf *buf = &priv->mgmt_rx[counter]; islpci_free_memory()
763 for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { islpci_free_memory()
764 if (priv->pci_map_rx_address[counter]) islpci_free_memory()
766 priv->pci_map_rx_address[counter], islpci_free_memory()
769 priv->pci_map_rx_address[counter] = 0; islpci_free_memory()
771 if (priv->data_low_rx[counter]) islpci_free_memory()
772 dev_kfree_skb(priv->data_low_rx[counter]); islpci_free_memory()
773 priv->data_low_rx[counter] = NULL; islpci_free_memory()
868 /* init the queue read locks, process wait counter */ islpci_setup()
/linux-4.1.27/fs/
H A Deventfd.c33 * side eventfd_signal() also, adds to the "count" counter and
41 * eventfd_signal - Adds @n to the eventfd counter.
43 * @n: [in] Value of the counter to be added to the eventfd internal counter.
47 * allow sleeping. In this function we allow the counter to reach the ULLONG_MAX
51 * Returns the amount by which the counter was incrememnted. This will be less
52 * than @n if the counter has overflowed.
144 * eventfd_ctx_remove_wait_queue - Read the current counter and removes wait queue.
147 * @cnt: [out] Pointer to the 64-bit counter value.
154 * queue head, and read/reset the counter value.
173 * eventfd_ctx_read - Reads the eventfd counter or wait if it is zero.
176 * @cnt: [out] Pointer to the 64-bit counter value.
184 * counter becomes greater than zero.
379 * @count: Initial eventfd counter value.
/linux-4.1.27/include/linux/netfilter/ipset/
H A Dip_set.h286 ip_set_add_bytes(u64 bytes, struct ip_set_counter *counter) ip_set_add_bytes() argument
288 atomic64_add((long long)bytes, &(counter)->bytes); ip_set_add_bytes()
292 ip_set_add_packets(u64 packets, struct ip_set_counter *counter) ip_set_add_packets() argument
294 atomic64_add((long long)packets, &(counter)->packets); ip_set_add_packets()
298 ip_set_get_bytes(const struct ip_set_counter *counter) ip_set_get_bytes() argument
300 return (u64)atomic64_read(&(counter)->bytes); ip_set_get_bytes()
304 ip_set_get_packets(const struct ip_set_counter *counter) ip_set_get_packets() argument
306 return (u64)atomic64_read(&(counter)->packets); ip_set_get_packets()
310 ip_set_update_counter(struct ip_set_counter *counter, ip_set_update_counter() argument
316 ip_set_add_bytes(ext->bytes, counter); ip_set_update_counter()
317 ip_set_add_packets(ext->packets, counter); ip_set_update_counter()
320 mext->packets = ip_set_get_packets(counter); ip_set_update_counter()
321 mext->bytes = ip_set_get_bytes(counter); ip_set_update_counter()
363 ip_set_put_counter(struct sk_buff *skb, struct ip_set_counter *counter) ip_set_put_counter() argument
366 cpu_to_be64(ip_set_get_bytes(counter))) || ip_set_put_counter()
368 cpu_to_be64(ip_set_get_packets(counter))); ip_set_put_counter()
372 ip_set_init_counter(struct ip_set_counter *counter, ip_set_init_counter() argument
376 atomic64_set(&(counter)->bytes, (long long)(ext->bytes)); ip_set_init_counter()
378 atomic64_set(&(counter)->packets, (long long)(ext->packets)); ip_set_init_counter()
/linux-4.1.27/arch/powerpc/platforms/cell/
H A Dpmu.c70 * Physical counter registers.
71 * Each physical counter can act as one 32-bit counter or two 16-bit counters.
81 /* Read the latch or the actual counter, whichever is newer. */ cbe_read_phys_ctr()
99 /* Writing to a counter only writes to a hardware latch. cbe_write_phys_ctr()
100 * The new value is not propagated to the actual counter cbe_write_phys_ctr()
121 * "Logical" counter registers.
123 * current size of the counter. Counters 4 - 7 are always 16-bit.
162 * Each "logical" counter has a corresponding control register.
268 * Get/set the size of a physical counter to either 16 or 32 bits.
/linux-4.1.27/drivers/net/ethernet/freescale/
H A Dfec_ptp.c140 * TCSR register to be cleared before the first compare counter fec_ptp_enable_pps()
150 /* Dummy read counter to update the counter */ fec_ptp_enable_pps()
164 /* Convert the ptp local counter to 1588 timestamp */ fec_ptp_enable_pps()
179 * counter is calculated and written into TCCR register. To avoid fec_ptp_enable_pps()
188 * ptp counter, which maybe cause 32-bit wrap. Since the fec_ptp_enable_pps()
228 * fec_ptp_read - read raw cycle counter (to be used by time counter)
232 * cyclecounter structure used to construct a ns counter from the
254 * fec_ptp_start_cyclecounter - create the cycle counter from hw
258 * structures for use in generated a ns counter from the arbitrary
272 /* 1ns counter */ fec_ptp_start_cyclecounter()
275 /* use 31-bit timer counter */ fec_ptp_start_cyclecounter()
287 /* reset the ns time counter */ fec_ptp_start_cyclecounter()
298 * Adjust the frequency of the ptp cycle counter by the
368 * @delta: offset to adjust the cycle counter by
412 * @ts: the timespec containing the new time for the cycle counter
425 u32 counter; fec_ptp_settime() local
436 * Update the counter with the masked value. fec_ptp_settime()
438 counter = ns & fep->cc.mask; fec_ptp_settime()
441 writel(counter, fep->hwp + FEC_ATIME); fec_ptp_settime()
539 * because ENET just support 32bit counter, will timeout in 4s
610 * This function check the pps event and reload the timer compare counter.
628 /* Update the counter; */ fec_ptp_check_pps_event()
/linux-4.1.27/drivers/clk/qcom/
H A Dclk-rcg.h39 * struct mn - M/N:D counter
40 * @mnctr_en_bit: bit to enable mn counter
41 * @mnctr_reset_bit: bit to assert mn counter reset
42 * @mnctr_mode_shift: lowest bit of mn counter mode field
86 * @mn: mn counter
120 * @mn: mn counter (banked)
/linux-4.1.27/arch/mips/loongson/common/cs5536/
H A Dcs5536_mfgpt.c40 /* disable counter */ disable_mfgpt0_counter()
47 /* enable counter, comparator2 to event mode, 14.318MHz clock */ enable_mfgpt0_counter()
62 outw(0, MFGPT0_CNT); /* set counter to 0 */ init_mfgpt_timer()
149 * running counter:
169 * the counter may underflow between the last point where mfgpt_read()
181 * The timer counter underflows, but we haven't handled the resulting mfgpt_read()
/linux-4.1.27/arch/arm64/kernel/vdso/
H A Dgettimeofday.S57 /* Acquire the sequence counter and get the timespec. */
114 /* Check the sequence counter. */
134 /* Check the sequence counter. */
208 * Read the current time from the architected counter.
212 * - w9 = vDSO sequence counter
225 /* Read the virtual counter. */
/linux-4.1.27/arch/hexagon/include/asm/
H A Datomic.h40 : "r" (&v->counter), "r" (new) atomic_set()
51 #define atomic_read(v) ((v)->counter)
58 #define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
90 : "r" (&v->counter), "r" (old), "r" (new) atomic_cmpxchg()
108 : "r" (&v->counter), "r" (i) \
124 : "r" (&v->counter), "r" (i) \
/linux-4.1.27/drivers/input/misc/
H A Dpcspkr.c48 /* set command for counter 2, 2 byte write */ pcspkr_event()
53 /* enable counter 2 */ pcspkr_event()
56 /* disable counter 2 */ pcspkr_event()
/linux-4.1.27/arch/mips/bcm47xx/
H A Dtime.c40 * Use deterministic values for initial counter interrupt plat_time_init()
41 * so that calibrate delay avoids encountering a counter wrap. plat_time_init()
79 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */ plat_time_init()
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h171 * @counter: The counter to configure. Range 0..3.
173 * @clear_on_read: When asserted, any read of the performance counter
174 * clears the counter.
176 * @note The routine does not clear the counter.
178 void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
181 * Read the given L2 Cache performance counter. The counter must be configured
184 * @counter: The counter to configure. Range 0..3.
186 * Returns The current counter value.
188 uint64_t cvmx_l2c_read_perf(uint32_t counter);
/linux-4.1.27/arch/mn10300/unit-asb2303/include/unit/
H A Dtimex.h19 * jiffies counter specifications
88 * timestamp counter specifications
100 /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time startup_timestamp_counter()
/linux-4.1.27/arch/mn10300/unit-asb2305/include/unit/
H A Dtimex.h19 * jiffies counter specifications
88 * timestamp counter specifications
100 /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time startup_timestamp_counter()
/linux-4.1.27/drivers/isdn/hisax/
H A Dhisax_fcpcipnp.h42 int tx_cnt; /* B-Channel transmit counter */
/linux-4.1.27/drivers/rtc/
H A Drtc-dm355evm.c2 * rtc-dm355evm.c - access battery-backed counter in MSP430 firmware
22 * a 1 Hz counter. When a backup battery is supplied, that makes a
27 * counter bytes atomically: the count may increment in the middle
45 * Read LSB(0) to MSB(3) bytes. Defend against the counter dm355evm_rtc_read_time()
H A Drtc-au1xxx.c2 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
98 /* wait until the hardware allows writes to the counter reg */ au1xtoy_rtc_probe()
125 MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
/linux-4.1.27/drivers/staging/skein/
H A Dskein_base.c215 /* run Threefish in "counter mode" to generate output */ skein_256_final()
216 /* zero out b[], so it can hold the counter */ skein_256_final()
218 /* keep a local copy of counter mode "key" */ skein_256_final()
221 /* build the counter block */ skein_256_final()
224 /* run "counter mode" */ skein_256_final()
233 /* restore the counter mode key for next time */ skein_256_final()
440 /* run Threefish in "counter mode" to generate output */ skein_512_final()
441 /* zero out b[], so it can hold the counter */ skein_512_final()
443 /* keep a local copy of counter mode "key" */ skein_512_final()
446 /* build the counter block */ skein_512_final()
449 /* run "counter mode" */ skein_512_final()
458 /* restore the counter mode key for next time */ skein_512_final()
660 /* run Threefish in "counter mode" to generate output */ skein_1024_final()
661 /* zero out b[], so it can hold the counter */ skein_1024_final()
663 /* keep a local copy of counter mode "key" */ skein_1024_final()
666 /* build the counter block */ skein_1024_final()
669 /* run "counter mode" */ skein_1024_final()
678 /* restore the counter mode key for next time */ skein_1024_final()
767 /* run Threefish in "counter mode" to generate output */ skein_256_output()
768 /* zero out b[], so it can hold the counter */ skein_256_output()
770 /* keep a local copy of counter mode "key" */ skein_256_output()
773 /* build the counter block */ skein_256_output()
776 /* run "counter mode" */ skein_256_output()
785 /* restore the counter mode key for next time */ skein_256_output()
804 /* run Threefish in "counter mode" to generate output */ skein_512_output()
805 /* zero out b[], so it can hold the counter */ skein_512_output()
807 /* keep a local copy of counter mode "key" */ skein_512_output()
810 /* build the counter block */ skein_512_output()
813 /* run "counter mode" */ skein_512_output()
822 /* restore the counter mode key for next time */ skein_512_output()
841 /* run Threefish in "counter mode" to generate output */ skein_1024_output()
842 /* zero out b[], so it can hold the counter */ skein_1024_output()
844 /* keep a local copy of counter mode "key" */ skein_1024_output()
847 /* build the counter block */ skein_1024_output()
850 /* run "counter mode" */ skein_1024_output()
859 /* restore the counter mode key for next time */ skein_1024_output()
/linux-4.1.27/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h114 /* Cumulative counter of released packets per AC */
117 /* Cumulative counter of freed packets per HLID */
120 /* Cumulative counter of released Voice memory blocks */
152 /* Cumulative counter of total released mem blocks since FW-reset */
/linux-4.1.27/include/linux/platform_data/
H A Dkeypad-ep93xx.h18 * @prescale: row/column counter pre-scaler load value
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dclksupport.h15 * RTC_COUNTER_ADDR - contains the address of the counter
/linux-4.1.27/arch/arm/plat-omap/
H A Dcounter_32k.c25 #include <plat/counter-32k.h>
27 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
36 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
74 * omap_init_clocksource_32k - setup and register counter 32k as a
/linux-4.1.27/kernel/gcov/
H A Dgcc_3_4.c32 * @n_ctrs: number of values per counter type belonging to this function
44 * struct gcov_ctr_info - profiling data per counter type
45 * @num: number of counter values for this type
46 * @values: array of counter values for this type
47 * @merge: merge function for counter values of this type (unused)
66 * @ctr_mask: mask specifying which counter types are active
67 * @counts: counter data per counter type
146 * Determine whether a counter is active. Based on gcc magic. Doesn't change
264 /* Duplicate counter arrays. */ gcov_info_dup()
301 * @ctr_type: counter type
308 * for each counter type
314 * for each counter type
329 * @type: counter type
331 * @num_types: number of counter types
453 /* Advance to next counter type */ gcov_iter_next()
/linux-4.1.27/net/batman-adv/
H A Dtypes.h405 * @BATADV_CNT_TX: transmitted payload traffic packet counter
406 * @BATADV_CNT_TX_BYTES: transmitted payload traffic bytes counter
407 * @BATADV_CNT_TX_DROPPED: dropped transmission payload traffic packet counter
408 * @BATADV_CNT_RX: received payload traffic packet counter
409 * @BATADV_CNT_RX_BYTES: received payload traffic bytes counter
410 * @BATADV_CNT_FORWARD: forwarded payload traffic packet counter
411 * @BATADV_CNT_FORWARD_BYTES: forwarded payload traffic bytes counter
412 * @BATADV_CNT_MGMT_TX: transmitted routing protocol traffic packet counter
413 * @BATADV_CNT_MGMT_TX_BYTES: transmitted routing protocol traffic bytes counter
414 * @BATADV_CNT_MGMT_RX: received routing protocol traffic packet counter
415 * @BATADV_CNT_MGMT_RX_BYTES: received routing protocol traffic bytes counter
416 * @BATADV_CNT_FRAG_TX: transmitted fragment traffic packet counter
417 * @BATADV_CNT_FRAG_TX_BYTES: transmitted fragment traffic bytes counter
418 * @BATADV_CNT_FRAG_RX: received fragment traffic packet counter
419 * @BATADV_CNT_FRAG_RX_BYTES: received fragment traffic bytes counter
420 * @BATADV_CNT_FRAG_FWD: forwarded fragment traffic packet counter
421 * @BATADV_CNT_FRAG_FWD_BYTES: forwarded fragment traffic bytes counter
422 * @BATADV_CNT_TT_REQUEST_TX: transmitted tt req traffic packet counter
423 * @BATADV_CNT_TT_REQUEST_RX: received tt req traffic packet counter
424 * @BATADV_CNT_TT_RESPONSE_TX: transmitted tt resp traffic packet counter
425 * @BATADV_CNT_TT_RESPONSE_RX: received tt resp traffic packet counter
426 * @BATADV_CNT_TT_ROAM_ADV_TX: transmitted tt roam traffic packet counter
427 * @BATADV_CNT_TT_ROAM_ADV_RX: received tt roam traffic packet counter
428 * @BATADV_CNT_DAT_GET_TX: transmitted dht GET traffic packet counter
429 * @BATADV_CNT_DAT_GET_RX: received dht GET traffic packet counter
430 * @BATADV_CNT_DAT_PUT_TX: transmitted dht PUT traffic packet counter
431 * @BATADV_CNT_DAT_PUT_RX: received dht PUT traffic packet counter
433 * counter
434 * @BATADV_CNT_NC_CODE: transmitted nc-combined traffic packet counter
435 * @BATADV_CNT_NC_CODE_BYTES: transmitted nc-combined traffic bytes counter
436 * @BATADV_CNT_NC_RECODE: transmitted nc-recombined traffic packet counter
437 * @BATADV_CNT_NC_RECODE_BYTES: transmitted nc-recombined traffic bytes counter
438 * @BATADV_CNT_NC_BUFFER: counter for packets buffered for later nc decoding
439 * @BATADV_CNT_NC_DECODE: received and nc-decoded traffic packet counter
440 * @BATADV_CNT_NC_DECODE_BYTES: received and nc-decoded traffic bytes counter
442 * counter
443 * @BATADV_CNT_NC_SNIFFED: counter for nc-decoded packets received in promisc
495 * @ogm_append_cnt: counter of number of OGMs containing the local tt diff
639 * @num_want_all_ipv4: counter for items in want_all_ipv4_list
640 * @num_want_all_ipv6: counter for items in want_all_ipv6_list
722 * @frag_seqno: incremental counter to identify chains of egress fragments
998 * @counter: number of allowed roaming events per client within a single
1005 atomic_t counter; member in struct:batadv_tt_roam_node
1088 * @num_packets: counter for bcast packet retransmission
/linux-4.1.27/arch/x86/realmode/rm/
H A Dwakemain.c21 outb(div, 0x42); /* LSB of counter */ beep()
23 outb(div >> 8, 0x42); /* MSB of counter */ beep()
/linux-4.1.27/arch/mips/cobalt/
H A Dtime.c38 * MIPS counter frequency is measured during a 100msec interval plat_time_init()
53 printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency); plat_time_init()
/linux-4.1.27/arch/mips/include/asm/sgi/
H A Dioc.h81 volatile u8 tcnt0; /* counter 0 */
83 volatile u8 tcnt1; /* counter 1 */
85 volatile u8 tcnt2; /* counter 2 */
100 #define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
101 #define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
102 #define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
103 #define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
113 * This is the constant we're using for calibrating the counter.
/linux-4.1.27/Documentation/prctl/
H A Ddisable-tsc-ctxt-sw-stress-test.c22 /* Get/set the process' ability to use the timestamp counter instruction */
26 # define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
H A Ddisable-tsc-on-off-stress-test.c22 /* Get/set the process' ability to use the timestamp counter instruction */
26 # define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
H A Ddisable-tsc-test.c17 /* Get/set the process' ability to use the timestamp counter instruction */
21 # define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
/linux-4.1.27/include/clocksource/
H A Darm_arch_timer.h36 #define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
37 #define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
/linux-4.1.27/drivers/staging/vt6656/
H A Dcard.c28 * vnt_get_current_tsf - Read Current NIC TSF counter
29 * vnt_get_next_tbtt - Calculate Next Beacon TSF counter
523 * Description: Sync. TSF counter to BSS
558 * Description: Read NIC TSF counter
559 * Get local TSF counter
565 * current_tsf - Current TSF counter
579 * Description: Clear NIC TSF counter
580 * Clear local TSF counter
600 * Description: Read NIC TSF counter
605 * tsf - Current TSF counter
608 * tsf - Current TSF counter
632 * Description: Set NIC TSF counter for first Beacon time
668 * Description: Sync NIC TSF counter for Beacon time
674 * tsf - Current TSF counter
/linux-4.1.27/drivers/staging/rtl8188eu/hal/
H A Dfw.c148 u32 counter = 0; _rtl88e_fw_free_to_go() local
155 } while (counter++ < POLLING_READY_TIMEOUT_COUNT); _rtl88e_fw_free_to_go()
157 if (counter >= POLLING_READY_TIMEOUT_COUNT) _rtl88e_fw_free_to_go()
166 counter = 0; _rtl88e_fw_free_to_go()
177 } while (counter++ < POLLING_READY_TIMEOUT_COUNT); _rtl88e_fw_free_to_go()
/linux-4.1.27/drivers/platform/x86/
H A Ddell-smo8800.c30 atomic_t counter; /* count after last read */ member in struct:smo8800_device
41 atomic_inc(&smo8800->counter); smo8800_interrupt_quick()
98 atomic_set(&smo8800->counter, 0); smo8800_misc_read()
100 (data = atomic_xchg(&smo8800->counter, 0))); smo8800_misc_read()
127 atomic_set(&smo8800->counter, 0); smo8800_misc_open()
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A Dxircom_cb.c90 /* transmit_used is the rotating counter that indicates which transmit
701 int counter; activate_receiver() local
714 counter = 10; activate_receiver()
715 while (counter > 0) { activate_receiver()
720 counter--; activate_receiver()
721 if (counter <= 0) activate_receiver()
731 counter = 10; activate_receiver()
732 while (counter > 0) { activate_receiver()
737 counter--; activate_receiver()
738 if (counter <= 0) activate_receiver()
755 int counter; deactivate_receiver() local
761 counter = 10; deactivate_receiver()
762 while (counter > 0) { deactivate_receiver()
767 counter--; deactivate_receiver()
768 if (counter <= 0) deactivate_receiver()
788 int counter; activate_transmitter() local
800 counter = 10; activate_transmitter()
801 while (counter > 0) { activate_transmitter()
806 counter--; activate_transmitter()
807 if (counter <= 0) activate_transmitter()
818 counter = 10; activate_transmitter()
819 while (counter > 0) { activate_transmitter()
824 counter--; activate_transmitter()
825 if (counter <= 0) activate_transmitter()
842 int counter; deactivate_transmitter() local
848 counter = 20; deactivate_transmitter()
849 while (counter > 0) { deactivate_transmitter()
854 counter--; deactivate_transmitter()
855 if (counter <= 0) deactivate_transmitter()
/linux-4.1.27/drivers/infiniband/hw/ipath/
H A Dipath_user_sdma.c58 u32 counter; /* sdma pkts queued counter for this entry */ member in struct:ipath_user_sdma_pkt
90 u32 counter; member in struct:ipath_user_sdma_queue
109 pq->counter = 0; ipath_user_sdma_queue_create()
163 u32 counter, size_t offset, ipath_user_sdma_init_header()
169 pkt->counter = counter; ipath_user_sdma_init_header()
367 /* free a packet list -- return counter value of last packet */ ipath_user_sdma_free_pkt_list()
407 u32 counter = pq->counter; ipath_user_sdma_queue_pkts() local
518 ipath_user_sdma_init_header(pkt, counter, 0, len, dma_mapped, ipath_user_sdma_queue_pkts()
529 counter++; ipath_user_sdma_queue_pkts()
585 u32 counter; ipath_user_sdma_queue_clean() local
589 counter = pkt->counter; ipath_user_sdma_queue_clean()
592 ipath_user_sdma_set_complete_counter(pq, counter); ipath_user_sdma_queue_clean()
837 pq->counter += ret; ipath_user_sdma_writev()
873 return pq->counter; ipath_user_sdma_inflight_counter()
162 ipath_user_sdma_init_header(struct ipath_user_sdma_pkt *pkt, u32 counter, size_t offset, size_t len, int dma_mapped, struct page *page, void *kvaddr, dma_addr_t dma_addr) ipath_user_sdma_init_header() argument
/linux-4.1.27/arch/sh/kernel/
H A Dhw_breakpoint.c42 * Install a perf counter breakpoint.
46 * Atomic: we hold the counter->ctx->lock and we only handle variables
73 * Uninstall the breakpoint contained in the given counter.
78 * Atomic: we hold the counter->ctx->lock and we only handle variables
312 * The counter may be concurrently released but that can only hw_breakpoint_handler()
314 * the breakpoint, use its callback, touch its counter hw_breakpoint_handler()
330 * bp can be NULL due to concurrent perf counter hw_breakpoint_handler()
/linux-4.1.27/scripts/
H A Dmarkup_oops.pl215 my $counter = 0;
257 $center = $counter;
260 $lines[$counter] = $line;
262 $counter = $counter + 1;
268 if ($counter == 0) {
306 while ($finish < $counter) {
/linux-4.1.27/drivers/infiniband/hw/ehca/
H A Dehca_cq.c129 u32 counter; ehca_create_cq() local
202 for (counter = 0; counter < param.act_pages; counter++) { ehca_create_cq()
224 "ehca_cq=%p cq_num=%x h_ret=%lli counter=%i " ehca_create_cq()
226 h_ret, counter, param.act_pages); ehca_create_cq()
231 if (counter == (param.act_pages - 1)) { ehca_create_cq()
245 "counter=%i act_pages=%i", ehca_create_cq()
247 h_ret, counter, param.act_pages); ehca_create_cq()
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
H A Dmmc.h29 /* When set, all counter are reset */
34 #define MMC_CNTRL_COUNTER_FREEZER 0x8 /* Freeze counter values to the
65 /* MMC RX counter registers */
/linux-4.1.27/drivers/staging/unisys/visorutil/
H A Dcharqueue.c101 int rc, counter = 0, c; visor_charqueue_dequeue_n() local
113 counter++; visor_charqueue_dequeue_n()
115 rc = counter; visor_charqueue_dequeue_n()
/linux-4.1.27/drivers/net/ethernet/brocade/bna/
H A Dbfa_cs.h84 /* Generic wait counter. */
108 /* Initialize a waiting counter. */
118 /* Wait for counter to reach zero */
/linux-4.1.27/arch/tile/kernel/
H A Dpmc.c54 * Get current overflow status of each performance counter,
55 * and auxiliary performance counter.
71 * Clear the status bit for the corresponding counter, if written
/linux-4.1.27/arch/s390/pci/
H A Dpci_debug.c45 atomic64_t *counter = &zdev->allocated_pages; pci_sw_counter_show() local
48 for (i = 0; i < ARRAY_SIZE(pci_sw_names); i++, counter++) pci_sw_counter_show()
50 atomic64_read(counter)); pci_sw_counter_show()
/linux-4.1.27/arch/mn10300/unit-asb2364/include/unit/
H A Dtimex.h19 * jiffies counter specifications
106 * timestamp counter specifications
112 /* Use 32-bit timestamp counter */
/linux-4.1.27/arch/avr32/kernel/
H A Dtime.c34 static struct clocksource counter = { variable in typeref:struct:clocksource
135 /* figure rate for counter */ time_init()
137 ret = clocksource_register_hz(&counter, counter_hz); time_init()
/linux-4.1.27/arch/alpha/oprofile/
H A Dop_model_ev4.c31 frequency, and set the frequency counter to LOW. The interrupts ev4_reg_setup()
32 for these "disabled" counter overflows are ignored by the ev4_reg_setup()
42 /* EV4 can not read or write its counter registers. The only ev4_reg_setup()
/linux-4.1.27/kernel/trace/
H A Dtrace_clock.c61 * trace_jiffy_clock(): Simply use jiffies as a clock counter.
130 * trace_clock_counter(): simply an atomic counter.
131 * Use the trace_counter "counter" for cases where you do not care
/linux-4.1.27/sound/soc/atmel/
H A Datmel-pcm.h46 unsigned int xcr; /* PDC recv/trans counter */
48 unsigned int xncr; /* PDC next recv/trans counter */
72 int pdc_xfer_size; /* PDC counter increment in bytes */
/linux-4.1.27/drivers/infiniband/hw/nes/
H A Dnes_utils.c62 u32 counter; nes_set_pau() local
67 for (counter = 0; counter < NES_PAU_COUNTER; counter++) { nes_set_pau()
75 if (counter == NES_PAU_COUNTER) { nes_set_pau()
416 u32 counter; nes_write_1G_phy_reg() local
420 for (counter = 0; counter < 100 ; counter++) { nes_write_1G_phy_reg()
443 u32 counter; nes_read_1G_phy_reg() local
450 for (counter = 0; counter < 100 ; counter++) { nes_read_1G_phy_reg()
477 u32 counter; nes_write_10G_phy_reg() local
484 for (counter = 0; counter < 100 ; counter++) { nes_write_10G_phy_reg()
499 for (counter = 0; counter < 100 ; counter++) { nes_write_10G_phy_reg()
522 u32 counter; nes_read_10G_phy_reg() local
529 for (counter = 0; counter < 100 ; counter++) { nes_read_10G_phy_reg()
544 for (counter = 0; counter < 100 ; counter++) { nes_read_10G_phy_reg()
/linux-4.1.27/drivers/net/fddi/skfp/h/
H A Dcmtdef.h407 u_long mac_nobuf_counter ; /* MAC SW counter: no buffer */
408 u_long mac_r_restart_counter ; /* MAC SW counter: rx restarted */
456 u_long soft_err ; /* error counter */
457 u_long parity_err ; /* error counter */
458 u_long ebuf_err ; /* error counter */
459 u_long ebuf_cont ; /* continuous error counter */
460 u_long phyinv ; /* error counter */
461 u_long vsym_ctr ; /* error counter */
462 u_long mini_ctr ; /* error counter */
463 u_long tpc_exp ; /* error counter */
464 u_long np_err ; /* error counter */
465 u_long b_pcs ; /* error counter */
466 u_long b_tpc ; /* error counter */
467 u_long b_tne ; /* error counter */
468 u_long b_qls ; /* error counter */
469 u_long b_ils ; /* error counter */
470 u_long b_hls ; /* error counter */
/linux-4.1.27/arch/m68k/fpsp040/
H A Ddecbin.S145 moveql #ESTRT,%d3 |counter to pick up digits
180 | (*) d1: lword counter
191 moveql #1,%d1 |word counter, init to 1
207 moveql #FSTRT,%d3 |counter to pick up digits
274 | (*) d5: lword counter
296 moveql #1,%d5 |init lword counter
300 addql #1,%d5 |inc lword counter
304 moveql #7,%d2 |init digit counter
309 addql #1,%d1 |inc digit counter
312 movel %d1,%d0 |copy counter to d2
328 moveql #3,%d2 |init d2 to count bits in counter
343 clrl %d1 |clr counter
348 addql #8,%d1 |inc counter by 8
352 moveql #7,%d2 |init digit counter
357 addql #1,%d1 |inc digit counter
360 movel %d1,%d0 |copy counter to d0
376 moveql #3,%d2 |init d2 to count bits in counter
/linux-4.1.27/drivers/net/wan/
H A Dx25_asy.h27 int rcount; /* received chars counter */
/linux-4.1.27/drivers/net/wireless/ti/wl18xx/
H A Dwl18xx.h116 /* Cumulative counter of released packets per AC */
119 /* Cumulative counter of freed packets per HLID */
122 /* Cumulative counter of released Voice memory blocks */
154 /* Cumulative counter of total released mem blocks since FW-reset */
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A D3945-rs.c137 win->counter = 0; il3945_clear_win()
163 if (!rs_sta->win[i].counter) il3945_rate_scale_flush_wins()
169 rs_sta->win[i].counter, i); il3945_rate_scale_flush_wins()
275 * subtract "1" from the success counter (this is the main reason il3945_collect_tx_data()
279 if (win->counter >= RATE_MAX_WINDOW) { il3945_collect_tx_data()
282 win->counter = RATE_MAX_WINDOW - 1; il3945_collect_tx_data()
290 /* Increment frames-attempted counter */ il3945_collect_tx_data()
291 win->counter++; il3945_collect_tx_data()
307 if (win->counter > 0) il3945_collect_tx_data()
309 128 * (100 * win->success_counter) / win->counter; il3945_collect_tx_data()
313 fail_count = win->counter - win->success_counter; il3945_collect_tx_data()
690 fail_count = win->counter - win->success_counter; il3945_rs_get_rate()
697 "counter: %d, success_counter: %d, " il3945_rs_get_rate()
698 "expected_tpt is %sNULL\n", idx, win->counter, il3945_rs_get_rate()
847 sprintf(buff + desc, "counter=%d success=%d %%=%d\n", il3945_sta_dbgfs_stats_table_read()
848 lq_sta->win[j].counter, il3945_sta_dbgfs_stats_table_read()
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Dmce.h14 __u64 tsc; /* cpu time stamp counter */
/linux-4.1.27/arch/x86/um/asm/
H A Dprocessor_32.h52 * instruction pointer ("program counter"). Stolen
/linux-4.1.27/arch/sh/lib64/
H A Dudelay.c19 * The active part of our cycle counter is only 32-bits wide, and
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dperfctr.h19 * Once enabled, performance counter state is retained until the
25 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
26 * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
32 * with zero and the user counter accumulator pointers and

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