Searched refs:corerev (Results 1 - 20 of 20) sorted by relevance

/linux-4.1.27/drivers/net/wireless/brcm80211/include/
H A Dchipcommon.h27 u32 corecontrol; /* corerev >= 1 */
31 u32 otpstatus; /* 0x10, corerev >= 10 */
34 u32 otplayout; /* corerev >= 23 */
61 u32 gpiopullup; /* 0x58, corerev >= 20 */
62 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
70 /* GPIO events corerev >= 11 */
77 /* GPIO events corerev >= 11 */
80 /* GPIO based LED powersave registers corerev >= 16 */
90 u32 clkdiv; /* corerev >= 3 */
91 u32 gpiodebugsel; /* corerev >= 28 */
94 /* pll delay registers (corerev >= 4) */
97 u32 slow_clk_ctl; /* 5 < corerev < 10 */
100 /* Instaclock registers (corerev >= 10) */
105 /* Indirect backplane access (corerev >= 22) */
113 /* More clock dividers (corerev >= 32) */
120 /* ExtBus control registers (corerev >= 3) */
136 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
156 /* SROM interface (corerev >= 32) */
162 /* Clock control and hardware workarounds (corerev >= 20) */
176 u8 PAD[248]; /* corerev >= 1 */
188 /* save/restore, corerev >= 48 */
195 /* PMU registers (corerev >= 20) */
222 u32 pmustrapopt; /* 0x668, corerev >= 28 */
238 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
284 #define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmfmac/
H A Dcommon.c68 ri->corerev = le32_to_cpu(revinfo.corerev); brcmf_c_preinit_dcmds()
H A Dchip.c150 /* bankidx and bankinfo reg defines corerev >= 8 */
199 u32 pwrctl; /* corerev >= 2 */
201 u32 sr_control; /* corerev >= 15 */
202 u32 sr_status; /* corerev >= 15 */
203 u32 sr_address; /* corerev >= 15 */
204 u32 sr_data; /* corerev >= 15 */
H A Dcore.h88 u32 corerev; member in struct:brcmf_rev_info
H A Dfwil_types.h549 * @corerev: core revision.
568 __le32 corerev; member in struct:brcmf_rev_info_le
H A Dcore.c960 seq_printf(s, "corerev: %u\n", ri->corerev); brcmf_revinfo_read()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/
H A Dpmu.c73 /* PMU corerev and chip specific PLL controls.
74 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
H A Dmain.c252 /* Starting corerev for the fifo size table */
289 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
291 /* corerev 18: */
293 /* corerev 19: */
295 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
297 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
299 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
301 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
303 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
305 /* corerev 25: */
307 /* corerev 26: */
309 /* corerev 27: */
311 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
723 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { brcms_c_ucode_bsinit()
728 "%s: wl%d: unsupported phy in corerev %d\n", brcms_c_ucode_bsinit()
730 wlc_hw->corerev); brcms_c_ucode_bsinit()
732 if (D11REV_IS(wlc_hw->corerev, 24)) { brcms_c_ucode_bsinit()
740 wlc_hw->corerev); brcms_c_ucode_bsinit()
743 "%s: wl%d: unsupported corerev %d\n", brcms_c_ucode_bsinit()
744 __func__, wlc_hw->unit, wlc_hw->corerev); brcms_c_ucode_bsinit()
1863 /* reject unsupported corerev */ brcms_c_isgoodchip()
1864 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) { brcms_c_isgoodchip()
1866 wlc_hw->corerev); brcms_c_isgoodchip()
1942 * it operates on different registers depending on corerev and boardflag.
1961 if (D11REV_GE(wlc_hw->corerev, 18)) brcms_b_radio_read_hwdisabled()
2043 if (D11REV_GE(wlc_hw->corerev, 18)) brcms_b_corereset()
2288 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { brcms_ucode_download()
2295 "%s: wl%d: unsupported phy in corerev %d\n", brcms_ucode_download()
2296 __func__, wlc_hw->unit, wlc_hw->corerev); brcms_ucode_download()
2297 } else if (D11REV_IS(wlc_hw->corerev, 24)) { brcms_ucode_download()
2304 "%s: wl%d: unsupported phy in corerev %d\n", brcms_ucode_download()
2305 __func__, wlc_hw->unit, wlc_hw->corerev); brcms_ucode_download()
3218 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { brcms_b_coreinit()
3222 brcms_err(core, "%s: wl%d: unsupported phy in corerev" brcms_b_coreinit()
3224 wlc_hw->corerev); brcms_b_coreinit()
3225 } else if (D11REV_IS(wlc_hw->corerev, 24)) { brcms_b_coreinit()
3229 brcms_err(core, "%s: wl%d: unsupported phy in corerev" brcms_b_coreinit()
3231 wlc_hw->corerev); brcms_b_coreinit()
3233 brcms_err(core, "%s: wl%d: unsupported corerev %d\n", brcms_b_coreinit()
3234 __func__, wlc_hw->unit, wlc_hw->corerev); brcms_b_coreinit()
3314 /* tell the ucode the corerev */ brcms_b_coreinit()
3315 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); brcms_b_coreinit()
4464 wlc_hw->corerev = core->id.rev; brcms_b_attach()
4466 /* validate chip, chiprev and corerev */ brcms_b_attach()
4530 wlc->pub->corerev = wlc_hw->corerev; brcms_b_attach()
4550 sha_params.corerev = wlc_hw->corerev; brcms_b_attach()
4588 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 || brcms_b_attach()
4589 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) > brcms_b_attach()
4592 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)]; brcms_b_attach()
H A Ddebug.c86 "corerev 0x%x\n" brcms_debugfs_hardware_read()
H A Dpub.h150 uint corerev; /* core revision */ member in struct:brcms_pub
H A Dd11.h114 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
1082 /* Location where the ucode expects the corerev */
1333 /* Disable Slow clock request, for corerev < 11 */
H A Dmain.h324 uint corerev; /* core revision */ member in struct:brcms_hardware
/linux-4.1.27/include/linux/bcma/
H A Dbcma_driver_chipcommon.h54 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
87 #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
120 #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
200 #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
205 #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
289 /* NAND flash registers for BCM4706 (corerev = 31) */
360 #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
366 /* NAND flash MLC controller registers (corerev >= 38) */
/linux-4.1.27/include/linux/ssb/
H A Dssb_driver_chipcommon.h59 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
87 #define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
103 #define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
135 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
140 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/phy/
H A Dphy_cmn.c185 if ((D11REV_GE(pi->sh->corerev, 24)) || read_radio_reg()
186 (D11REV_IS(pi->sh->corerev, 22) read_radio_reg()
201 if ((D11REV_GE(pi->sh->corerev, 24)) || write_radio_reg()
202 (D11REV_IS(pi->sh->corerev, 22) write_radio_reg()
223 if (D11REV_GE(pi->sh->corerev, 24)) { read_radio_id()
375 sh->corerev = shp->corerev; wlc_phy_shared_attach()
438 if (D11REV_IS(sh->corerev, 4)) wlc_phy_attach()
788 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) wlc_phy_init()
1014 if (D11REV_GE(pi->sh->corerev, 11)) wlc_phy_do_dummy_tx()
2158 if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) { wlc_phy_ant_rxdiv_set()
2536 if ((pi->sh->corerev >= 11) wlc_phy_rssi_compute()
H A Dphy_hal.h168 uint corerev; member in struct:shared_phy_params
H A Dphy_int.h492 uint corerev; member in struct:shared_phy
H A Dphy_n.c17676 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) { wlc_phy_txpwrctrl_pwr_setup_nphy()
17692 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) wlc_phy_txpwrctrl_pwr_setup_nphy()
17808 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) { wlc_phy_txpwrctrl_pwr_setup_nphy()
17828 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) wlc_phy_txpwrctrl_pwr_setup_nphy()
21408 if (D11REV_IS(pi->sh->corerev, 16)) { wlc_phy_classifier_nphy()
21421 if (D11REV_IS(pi->sh->corerev, 16) && !suspended) wlc_phy_classifier_nphy()
28235 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) { wlc_phy_txpower_recalc_target_nphy()
28243 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) wlc_phy_txpower_recalc_target_nphy()
/linux-4.1.27/drivers/net/wireless/b43/
H A Db43.h48 #define B43_MMIO_MAC_HW_CAP 0x15C /* MAC capabilities (corerev >= 13) */
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dbgmac.c1052 /* Request Misc PLL for corerev > 2 */ bgmac_chip_reset()

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