/linux-4.1.27/sound/pci/rme9652/ |
H A D | rme9652.c | 173 #define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS) 209 u32 control_register; /* cached value */ member in struct:snd_rme9652 361 i = rme9652->control_register & RME9652_latency; rme9652_compute_period_size() 438 s->control_register |= (RME9652_IE | RME9652_start_bit); rme9652_start() 439 rme9652_write(s, RME9652_control_register, s->control_register); rme9652_start() 444 s->control_register &= ~(RME9652_start_bit | RME9652_IE); rme9652_stop() 445 rme9652_write(s, RME9652_control_register, s->control_register); rme9652_stop() 467 s->control_register &= ~RME9652_latency; rme9652_set_interrupt_interval() 468 s->control_register |= rme9652_encode_latency(n); rme9652_set_interrupt_interval() 470 rme9652_write(s, RME9652_control_register, s->control_register); rme9652_set_interrupt_interval() 544 rme9652->control_register &= ~(RME9652_freq | RME9652_DS); rme9652_set_rate() 545 rme9652->control_register |= rate; rme9652_set_rate() 546 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_set_rate() 618 rme9652->control_register = rme9652_set_passthru() 626 rme9652->control_register); rme9652_set_passthru() 640 rme9652->control_register |= mask; rme9652_spdif_set_bit() 642 rme9652->control_register &= ~mask; rme9652_spdif_set_bit() 644 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_spdif_set_bit() 712 rme9652->control_register |= RME9652_SPDIF_RESET; rme9652_initialize_spdif_receiver() 864 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP); snd_rme9652_control_spdif_stream_put() 865 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val); snd_rme9652_control_spdif_stream_put() 891 if (rme9652->control_register & RME9652_ADAT1_INTERNAL) rme9652_adat1_in() 901 rme9652->control_register |= RME9652_ADAT1_INTERNAL; rme9652_set_adat1_input() 903 rme9652->control_register &= ~RME9652_ADAT1_INTERNAL; rme9652_set_adat1_input() 912 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_set_adat1_input() 962 return rme9652_decode_spdif_in(rme9652->control_register & rme9652_spdif_in() 970 rme9652->control_register &= ~RME9652_inp; rme9652_set_spdif_input() 971 rme9652->control_register |= rme9652_encode_spdif_in(in); rme9652_set_spdif_input() 977 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_set_spdif_input() 1027 return (rme9652->control_register & RME9652_opt_out) ? 1 : 0; rme9652_spdif_out() 1035 rme9652->control_register |= RME9652_opt_out; rme9652_set_spdif_output() 1037 rme9652->control_register &= ~RME9652_opt_out; rme9652_set_spdif_output() 1044 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_set_spdif_output() 1088 if (rme9652->control_register & RME9652_wsel) { rme9652_sync_mode() 1090 } else if (rme9652->control_register & RME9652_Master) { rme9652_sync_mode() 1103 rme9652->control_register &= rme9652_set_sync_mode() 1107 rme9652->control_register = rme9652_set_sync_mode() 1108 (rme9652->control_register & ~RME9652_wsel) | RME9652_Master; rme9652_set_sync_mode() 1111 rme9652->control_register |= rme9652_set_sync_mode() 1120 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_set_sync_mode() 1169 switch (rme9652->control_register & RME9652_SyncPref_Mask) { rme9652_sync_pref() 1187 rme9652->control_register &= ~RME9652_SyncPref_Mask; rme9652_set_sync_pref() 1190 rme9652->control_register |= RME9652_SyncPref_ADAT1; rme9652_set_sync_pref() 1193 rme9652->control_register |= RME9652_SyncPref_ADAT2; rme9652_set_sync_pref() 1196 rme9652->control_register |= RME9652_SyncPref_ADAT3; rme9652_set_sync_pref() 1199 rme9652->control_register |= RME9652_SyncPref_SPDIF; rme9652_set_sync_pref() 1207 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); rme9652_set_sync_pref() 1581 snd_iprintf(buffer, "Control register: %x\n", rme9652->control_register); snd_rme9652_proc_read() 1585 x = 1 << (6 + rme9652_decode_latency(rme9652->control_register & snd_rme9652_proc_read() 1595 if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) { snd_rme9652_proc_read() 1598 } else if (rme9652->control_register & RME9652_wsel) { snd_rme9652_proc_read() 1609 switch (rme9652->control_register & RME9652_SyncPref_Mask) { snd_rme9652_proc_read() 1629 (rme9652->control_register & RME9652_ADAT1_INTERNAL) ? snd_rme9652_proc_read() 1634 switch (rme9652_decode_spdif_in(rme9652->control_register & snd_rme9652_proc_read() 1650 if (rme9652->control_register & RME9652_opt_out) { snd_rme9652_proc_read() 1656 if (rme9652->control_register & RME9652_PRO) { snd_rme9652_proc_read() 1662 if (rme9652->control_register & RME9652_EMP) { snd_rme9652_proc_read() 1668 if (rme9652->control_register & RME9652_Dolby) { snd_rme9652_proc_read() 1816 rme9652->control_register = snd_rme9652_set_defaults() 1819 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register); snd_rme9652_set_defaults() 1976 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP); snd_rme9652_hw_params() 1977 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= rme9652->creg_spdif_stream); snd_rme9652_hw_params()
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H A D | hdsp.c | 466 u32 control_register; /* cached value */ member in struct:hdsp 1044 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); hdsp_compute_period_size() 1074 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); hdsp_start_audio() 1075 hdsp_write(s, HDSP_controlRegister, s->control_register); hdsp_start_audio() 1080 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); hdsp_stop_audio() 1081 hdsp_write(s, HDSP_controlRegister, s->control_register); hdsp_stop_audio() 1102 s->control_register &= ~HDSP_LatencyMask; hdsp_set_interrupt_interval() 1103 s->control_register |= hdsp_encode_latency(n); hdsp_set_interrupt_interval() 1105 hdsp_write(s, HDSP_controlRegister, s->control_register); hdsp_set_interrupt_interval() 1144 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { hdsp_set_rate() 1242 hdsp->control_register &= ~HDSP_FrequencyMask; hdsp_set_rate() 1243 hdsp->control_register |= rate_bits; hdsp_set_rate() 1244 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_rate() 1384 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; snd_hdsp_midi_input_read() 1386 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; snd_hdsp_midi_input_read() 1387 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); snd_hdsp_midi_input_read() 1404 if (!(hdsp->control_register & ie)) { snd_hdsp_midi_input_trigger() 1406 hdsp->control_register |= ie; snd_hdsp_midi_input_trigger() 1409 hdsp->control_register &= ~ie; snd_hdsp_midi_input_trigger() 1413 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); snd_hdsp_midi_input_trigger() 1637 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); snd_hdsp_control_spdif_stream_put() 1638 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); snd_hdsp_control_spdif_stream_put() 1666 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); hdsp_spdif_in() 1671 hdsp->control_register &= ~HDSP_SPDIFInputMask; hdsp_set_spdif_input() 1672 hdsp->control_register |= hdsp_encode_spdif_in(in); hdsp_set_spdif_input() 1673 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_spdif_input() 1724 return (hdsp->control_register & regmask) ? 1 : 0; hdsp_toggle_setting() 1730 hdsp->control_register |= regmask; hdsp_set_toggle_setting() 1732 hdsp->control_register &= ~regmask; hdsp_set_toggle_setting() 1733 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_toggle_setting() 1924 if (hdsp->control_register & HDSP_ClockModeMaster) hdsp_system_clock_mode() 1957 if (hdsp->control_register & HDSP_ClockModeMaster) { hdsp_clock_source() 1992 hdsp->control_register &= ~HDSP_ClockModeMaster; hdsp_set_clock_source() 1993 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_clock_source() 2028 hdsp->control_register |= HDSP_ClockModeMaster; hdsp_set_clock_source() 2029 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_clock_source() 2114 switch (hdsp->control_register & HDSP_DAGainMask) { hdsp_da_gain() 2128 hdsp->control_register &= ~HDSP_DAGainMask; hdsp_set_da_gain() 2131 hdsp->control_register |= HDSP_DAGainHighGain; hdsp_set_da_gain() 2134 hdsp->control_register |= HDSP_DAGainPlus4dBu; hdsp_set_da_gain() 2137 hdsp->control_register |= HDSP_DAGainMinus10dBV; hdsp_set_da_gain() 2143 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_da_gain() 2193 switch (hdsp->control_register & HDSP_ADGainMask) { hdsp_ad_gain() 2207 hdsp->control_register &= ~HDSP_ADGainMask; hdsp_set_ad_gain() 2210 hdsp->control_register |= HDSP_ADGainMinus10dBV; hdsp_set_ad_gain() 2213 hdsp->control_register |= HDSP_ADGainPlus4dBu; hdsp_set_ad_gain() 2216 hdsp->control_register |= HDSP_ADGainLowGain; hdsp_set_ad_gain() 2222 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_ad_gain() 2272 switch (hdsp->control_register & HDSP_PhoneGainMask) { hdsp_phone_gain() 2286 hdsp->control_register &= ~HDSP_PhoneGainMask; hdsp_set_phone_gain() 2289 hdsp->control_register |= HDSP_PhoneGain0dB; hdsp_set_phone_gain() 2292 hdsp->control_register |= HDSP_PhoneGainMinus6dB; hdsp_set_phone_gain() 2295 hdsp->control_register |= HDSP_PhoneGainMinus12dB; hdsp_set_phone_gain() 2301 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_phone_gain() 2355 switch (hdsp->control_register & HDSP_SyncRefMask) { hdsp_pref_sync_ref() 2376 hdsp->control_register &= ~HDSP_SyncRefMask; hdsp_set_pref_sync_ref() 2379 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ hdsp_set_pref_sync_ref() 2382 hdsp->control_register |= HDSP_SyncRef_ADAT2; hdsp_set_pref_sync_ref() 2385 hdsp->control_register |= HDSP_SyncRef_ADAT3; hdsp_set_pref_sync_ref() 2388 hdsp->control_register |= HDSP_SyncRef_SPDIF; hdsp_set_pref_sync_ref() 2391 hdsp->control_register |= HDSP_SyncRef_WORD; hdsp_set_pref_sync_ref() 2394 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; hdsp_set_pref_sync_ref() 2399 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_pref_sync_ref() 2980 switch (hdsp->control_register & HDSP_RPM_Inp12) { hdsp_rpm_input12() 3005 hdsp->control_register &= ~HDSP_RPM_Inp12; hdsp_set_rpm_input12() 3008 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB; hdsp_set_rpm_input12() 3013 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB; hdsp_set_rpm_input12() 3016 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB; hdsp_set_rpm_input12() 3019 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB; hdsp_set_rpm_input12() 3025 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_rpm_input12() 3065 switch (hdsp->control_register & HDSP_RPM_Inp34) { hdsp_rpm_input34() 3090 hdsp->control_register &= ~HDSP_RPM_Inp34; hdsp_set_rpm_input34() 3093 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB; hdsp_set_rpm_input34() 3098 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB; hdsp_set_rpm_input34() 3101 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB; hdsp_set_rpm_input34() 3104 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB; hdsp_set_rpm_input34() 3110 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_rpm_input34() 3141 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0; hdsp_rpm_bypass() 3157 hdsp->control_register |= HDSP_RPM_Bypass; hdsp_set_rpm_bypass() 3159 hdsp->control_register &= ~HDSP_RPM_Bypass; hdsp_set_rpm_bypass() 3160 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_rpm_bypass() 3193 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0; hdsp_rpm_disconnect() 3209 hdsp->control_register |= HDSP_RPM_Disconnect; hdsp_set_rpm_disconnect() 3211 hdsp->control_register &= ~HDSP_RPM_Disconnect; hdsp_set_rpm_disconnect() 3212 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); hdsp_set_rpm_disconnect() 3356 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); snd_hdsp_proc_read() 3397 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); snd_hdsp_proc_read() 3402 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); snd_hdsp_proc_read() 3532 if (hdsp->control_register & HDSP_RPM_Bypass) snd_hdsp_proc_read() 3536 if (hdsp->control_register & HDSP_RPM_Disconnect) snd_hdsp_proc_read() 3541 switch (hdsp->control_register & HDSP_RPM_Inp12) { snd_hdsp_proc_read() 3561 switch (hdsp->control_register & HDSP_RPM_Inp34) { snd_hdsp_proc_read() 3582 if (hdsp->control_register & HDSP_SPDIFOpticalOut) snd_hdsp_proc_read() 3587 if (hdsp->control_register & HDSP_SPDIFProfessional) snd_hdsp_proc_read() 3592 if (hdsp->control_register & HDSP_SPDIFEmphasis) snd_hdsp_proc_read() 3597 if (hdsp->control_register & HDSP_SPDIFNonAudio) snd_hdsp_proc_read() 3702 if (hdsp->control_register & HDSP_AnalogExtensionBoard) snd_hdsp_proc_read() 3772 hdsp->control_register = HDSP_ClockModeMaster | snd_hdsp_set_defaults() 3778 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); snd_hdsp_set_defaults() 3805 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); snd_hdsp_set_defaults() 3806 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); snd_hdsp_set_defaults() 3866 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; snd_hdsp_interrupt() 3867 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); snd_hdsp_interrupt() 3877 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; snd_hdsp_interrupt() 3878 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); snd_hdsp_interrupt() 4005 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); snd_hdsp_hw_params() 4006 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); snd_hdsp_hw_params() 5165 hdsp->control_register = 0; snd_hdsp_create() 5297 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); snd_hdsp_free() 5298 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); snd_hdsp_free()
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H A D | hdspm.c | 1005 u32 control_register; /* cached value */ member in struct:hdspm 1248 if (hdspm->control_register & HDSPM_QuadSpeed) hdspm_rate_multiplier() 1250 else if (hdspm->control_register & hdspm_rate_multiplier() 1462 n = hdspm_decode_latency(hdspm->control_register); hdspm_get_latency() 1507 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); hdspm_start_audio() 1508 hdspm_write(s, HDSPM_controlRegister, s->control_register); hdspm_start_audio() 1513 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); hdspm_stop_audio() 1514 hdspm_write(s, HDSPM_controlRegister, s->control_register); hdspm_stop_audio() 1560 s->control_register &= ~HDSPM_LatencyMask; hdspm_set_interrupt_interval() 1561 s->control_register |= hdspm_encode_latency(n); hdspm_set_interrupt_interval() 1563 hdspm_write(s, HDSPM_controlRegister, s->control_register); hdspm_set_interrupt_interval() 1647 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { hdspm_set_rate() 1749 hdspm->control_register &= ~HDSPM_FrequencyMask; hdspm_set_rate() 1750 hdspm->control_register |= rate_bits; hdspm_set_rate() 1751 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); hdspm_set_rate() 1917 hmidi->hdspm->control_register |= hmidi->ie; snd_hdspm_midi_input_read() 1919 hmidi->hdspm->control_register); snd_hdspm_midi_input_read() 1937 if (!(hdspm->control_register & hmidi->ie)) { snd_hdspm_midi_input_trigger() 1939 hdspm->control_register |= hmidi->ie; snd_hdspm_midi_input_trigger() 1942 hdspm->control_register &= ~hmidi->ie; snd_hdspm_midi_input_trigger() 1945 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); snd_hdspm_midi_input_trigger() 2533 if (hdspm->control_register & HDSPM_ClockModeMaster) hdspm_system_clock_mode() 2708 switch (hdspm->control_register & HDSPM_SyncRefMask) { hdspm_pref_sync_ref() 2726 switch (hdspm->control_register & HDSPM_SyncRefMask) { hdspm_pref_sync_ref() 2734 switch (hdspm->control_register & HDSPM_SyncRefMask) { hdspm_pref_sync_ref() 2813 hdspm->control_register &= ~HDSPM_SyncRefMask; hdspm_set_pref_sync_ref() 2818 hdspm->control_register |= HDSPM_SyncRef0; hdspm_set_pref_sync_ref() 2821 hdspm->control_register |= HDSPM_SyncRef1; hdspm_set_pref_sync_ref() 2824 hdspm->control_register |= hdspm_set_pref_sync_ref() 2828 hdspm->control_register |= HDSPM_SyncRef2; hdspm_set_pref_sync_ref() 2831 hdspm->control_register |= hdspm_set_pref_sync_ref() 2835 hdspm->control_register |= hdspm_set_pref_sync_ref() 2839 hdspm->control_register |= hdspm_set_pref_sync_ref() 2843 hdspm->control_register |= HDSPM_SyncRef3; hdspm_set_pref_sync_ref() 2846 hdspm->control_register |= hdspm_set_pref_sync_ref() 2857 hdspm->control_register &= ~HDSPM_SyncRefMask; hdspm_set_pref_sync_ref() 2863 hdspm->control_register |= HDSPM_SyncRef0; hdspm_set_pref_sync_ref() 2866 hdspm->control_register |= HDSPM_SyncRef1; hdspm_set_pref_sync_ref() 2869 hdspm->control_register |= hdspm_set_pref_sync_ref() 2880 hdspm->control_register |= HDSPM_SyncRef0; hdspm_set_pref_sync_ref() 2883 hdspm->control_register |= hdspm_set_pref_sync_ref() 2958 hdspm->control_register); hdspm_set_pref_sync_ref() 3209 reg = hdspm->control_register; hdspm_toggle_setting() 3223 reg = &(hdspm->control_register); hdspm_set_toggle_setting() 3280 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; hdspm_input_select() 3286 hdspm->control_register |= HDSPM_InputSelect0; hdspm_set_input_select() 3288 hdspm->control_register &= ~HDSPM_InputSelect0; hdspm_set_input_select() 3289 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); hdspm_set_input_select() 3342 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; hdspm_ds_wire() 3348 hdspm->control_register |= HDSPM_DS_DoubleWire; hdspm_set_ds_wire() 3350 hdspm->control_register &= ~HDSPM_DS_DoubleWire; hdspm_set_ds_wire() 3351 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); hdspm_set_ds_wire() 3404 if (hdspm->control_register & HDSPM_QS_DoubleWire) hdspm_qs_wire() 3406 if (hdspm->control_register & HDSPM_QS_QuadWire) hdspm_qs_wire() 3413 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); hdspm_set_qs_wire() 3418 hdspm->control_register |= HDSPM_QS_DoubleWire; hdspm_set_qs_wire() 3421 hdspm->control_register |= HDSPM_QS_QuadWire; hdspm_set_qs_wire() 3424 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); hdspm_set_qs_wire() 3558 if (hdspm->control_register & HDSPM_QuadSpeed) hdspm_madi_speedmode() 3560 if (hdspm->control_register & HDSPM_DoubleSpeed) hdspm_madi_speedmode() 3567 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); hdspm_set_madi_speedmode() 3572 hdspm->control_register |= HDSPM_DoubleSpeed; hdspm_set_madi_speedmode() 3575 hdspm->control_register |= HDSPM_QuadSpeed; hdspm_set_madi_speedmode() 3578 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); hdspm_set_madi_speedmode() 4765 control = hdspm->control_register; snd_hdspm_proc_read_tco() 4924 hdspm->control_register, hdspm->control2_register, snd_hdspm_proc_read_madi() 4937 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); snd_hdspm_proc_read_madi() 4942 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", snd_hdspm_proc_read_madi() 4943 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", snd_hdspm_proc_read_madi() 4944 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); snd_hdspm_proc_read_madi() 4947 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) snd_hdspm_proc_read_madi() 5081 hdspm->control_register, hdspm->control2_register, snd_hdspm_proc_read_aes32() 5094 control_register & HDSPM_LineOut) ? "on " : "off"); snd_hdspm_proc_read_aes32() 5099 control_register & HDSPM_clr_tms) ? "on" : "off", snd_hdspm_proc_read_aes32() 5101 control_register & HDSPM_Emphasis) ? "on" : "off", snd_hdspm_proc_read_aes32() 5103 control_register & HDSPM_Dolby) ? "on" : "off"); snd_hdspm_proc_read_aes32() 5117 hdspm->control_register & HDSPM_DS_DoubleWire? snd_hdspm_proc_read_aes32() 5120 hdspm->control_register & HDSPM_QS_DoubleWire? snd_hdspm_proc_read_aes32() 5122 hdspm->control_register & HDSPM_QS_QuadWire? snd_hdspm_proc_read_aes32() 5341 hdspm->control_register = snd_hdspm_set_defaults() 5350 hdspm->control_register = snd_hdspm_set_defaults() 5355 hdspm->control_register = snd_hdspm_set_defaults() 5364 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); snd_hdspm_set_defaults() 5450 hdspm->control_register &= ~hdspm->midi[i].ie; snd_hdspm_interrupt() 5452 hdspm->control_register); snd_hdspm_interrupt() 5647 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) snd_hdspm_hw_params() 5651 hdspm->control_register |= HDSPe_FLOAT_FORMAT; snd_hdspm_hw_params() 5653 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) snd_hdspm_hw_params() 5657 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; snd_hdspm_hw_params() 5659 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); snd_hdspm_hw_params() 6895 hdspm->control_register &= snd_hdspm_free() 6900 hdspm->control_register); snd_hdspm_free()
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/linux-4.1.27/sound/pci/echoaudio/ |
H A D | echoaudio_3g.c | 85 if (ctl != chip->comm_page->control_register || write_control_reg() 88 chip->comm_page->control_register = ctl; write_control_reg() 179 control_reg = le32_to_cpu(chip->comm_page->control_register); set_professional_spdif() 276 control_reg = le32_to_cpu(chip->comm_page->control_register); set_sample_rate() 333 control_reg = le32_to_cpu(chip->comm_page->control_register) & set_input_clock() 406 control_reg = le32_to_cpu(chip->comm_page->control_register); dsp_set_digital_mode()
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H A D | indigo_dsp.c | 117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { set_sample_rate() 122 chip->comm_page->control_register = cpu_to_le32(control_reg); set_sample_rate()
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H A D | indigo_express_dsp.c | 36 old_control_reg = le32_to_cpu(chip->comm_page->control_register); set_sample_rate() 66 chip->comm_page->control_register = cpu_to_le32(control_reg); set_sample_rate()
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H A D | indigodj_dsp.c | 117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { set_sample_rate() 122 chip->comm_page->control_register = cpu_to_le32(control_reg); set_sample_rate()
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H A D | mia_dsp.c | 138 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { set_sample_rate() 143 chip->comm_page->control_register = cpu_to_le32(control_reg); set_sample_rate()
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H A D | echoaudio_gml.c | 76 if (value != chip->comm_page->control_register || force) { write_control_reg() 79 chip->comm_page->control_register = value; write_control_reg() 160 control_reg = le32_to_cpu(chip->comm_page->control_register); set_professional_spdif()
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H A D | gina24_dsp.c | 182 control_reg = le32_to_cpu(chip->comm_page->control_register); set_sample_rate() 240 control_reg = le32_to_cpu(chip->comm_page->control_register) & set_input_clock() 314 control_reg = le32_to_cpu(chip->comm_page->control_register); dsp_set_digital_mode()
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H A D | layla24_dsp.c | 176 control_reg = le32_to_cpu(chip->comm_page->control_register); set_sample_rate() 254 control_reg = le32_to_cpu(chip->comm_page->control_register) & set_input_clock() 370 control_reg = le32_to_cpu(chip->comm_page->control_register); dsp_set_digital_mode()
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H A D | mona_dsp.c | 244 control_reg = le32_to_cpu(chip->comm_page->control_register); set_sample_rate() 309 control_reg = le32_to_cpu(chip->comm_page->control_register) & set_input_clock() 395 control_reg = le32_to_cpu(chip->comm_page->control_register); dsp_set_digital_mode()
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H A D | echo3g_dsp.c | 120 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); set_phantom_power()
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H A D | echoaudio_dsp.h | 688 u32 control_register; member in struct:comm_page
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/linux-4.1.27/drivers/crypto/ux500/cryp/ |
H A D | cryp.c | 108 * @control_register: The control register to be written later on. 112 u32 *control_register) cryp_set_configuration() 119 *control_register |= (cryp_config->keysize << CRYP_CR_KEYSIZE_POS); cryp_set_configuration() 125 cr_for_kse = *control_register; cryp_set_configuration() 151 *control_register |= cryp_set_configuration() 110 cryp_set_configuration(struct cryp_device_data *device_data, struct cryp_config *cryp_config, u32 *control_register) cryp_set_configuration() argument
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H A D | cryp.h | 266 u32 *control_register);
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H A D | cryp_core.c | 371 u32 control_register = CRYP_CR_DEFAULT; cryp_setup_context() local 403 &control_register); cryp_setup_context() 411 control_register = ctx->dev_ctx.cr; cryp_setup_context() 413 control_register = ctx->dev_ctx.cr; cryp_setup_context() 415 writel(control_register | cryp_setup_context()
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/linux-4.1.27/drivers/cpufreq/ |
H A D | acpi-cpufreq.c | 350 cmd.addr.io.port = perf->control_register.address; get_cur_val() 351 cmd.addr.io.bit_width = perf->control_register.bit_width; get_cur_val() 449 cmd.addr.io.port = perf->control_register.address; acpi_cpufreq_target() 450 cmd.addr.io.bit_width = perf->control_register.bit_width; acpi_cpufreq_target() 721 if (perf->control_register.space_id != perf->status_register.space_id) { acpi_cpufreq_cpu_init() 726 switch (perf->control_register.space_id) { acpi_cpufreq_cpu_init() 751 (u32) (perf->control_register.space_id)); acpi_cpufreq_cpu_init() 773 if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && acpi_cpufreq_cpu_init() 801 switch (perf->control_register.space_id) { acpi_cpufreq_cpu_init()
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H A D | ia64-acpi-cpufreq.c | 172 * control_register. processor_set_freq() 245 if ((data->acpi_data.control_register.space_id != acpi_cpufreq_cpu_init() 250 (u32) (data->acpi_data.control_register.space_id), acpi_cpufreq_cpu_init()
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H A D | powernow-k7.c | 326 if (acpi_processor_perf->control_register.space_id != powernow_acpi_init()
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H A D | powernow-k8.c | 757 control = data->acpi_data.control_register.space_id; powernow_k8_cpu_init_acpi()
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/linux-4.1.27/drivers/acpi/ |
H A D | processor_throttling.c | 453 * control_register acpi_processor_get_throttling_control() 462 "Invalid _PTC data (control_register)\n"); acpi_processor_get_throttling_control() 466 memcpy(&pr->throttling.control_register, obj.buffer.pointer, acpi_processor_get_throttling_control() 488 if ((throttling->control_register.bit_width + acpi_processor_get_throttling_control() 489 throttling->control_register.bit_offset) > 32) { acpi_processor_get_throttling_control() 814 switch (throttling->control_register.space_id) { acpi_write_throttling_state() 816 bit_width = throttling->control_register.bit_width; acpi_write_throttling_state() 817 bit_offset = throttling->control_register.bit_offset; acpi_write_throttling_state() 822 control_register.address, acpi_write_throttling_state() 832 (u32) (throttling->control_register.space_id)); acpi_write_throttling_state()
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H A D | processor_perflib.c | 251 * control_register acpi_processor_get_performance_control() 259 printk(KERN_ERR PREFIX "Invalid _PCT data (control_register)\n"); acpi_processor_get_performance_control() 263 memcpy(&pr->performance->control_register, obj.buffer.pointer, acpi_processor_get_performance_control()
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/linux-4.1.27/include/acpi/ |
H A D | processor.h | 107 struct acpi_pct_register control_register; member in struct:acpi_processor_performance 152 struct acpi_pct_register control_register; member in struct:acpi_processor_throttling
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H A D | actbl2.h | 931 struct acpi_generic_address control_register; member in struct:acpi_table_mchi 1266 struct acpi_generic_address control_register; member in struct:acpi_table_wdrt
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H A D | actbl1.h | 445 u32 control_register; member in struct:acpi_hest_ia_error_bank
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/linux-4.1.27/sound/pci/ |
H A D | als300.c | 139 int control_register; member in struct:snd_als300_substream_data 381 data->control_register = PLAYBACK_CONTROL; snd_als300_playback_open() 410 data->control_register = RECORD_CONTROL; snd_als300_capture_open() 506 reg = data->control_register; snd_als300_trigger()
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/linux-4.1.27/drivers/xen/ |
H A D | xen-acpi-processor.c | 226 xen_copy_pct_data(&(_pr->performance->control_register), push_pxx_to_hypervisor() 227 &dst_perf->control_register); push_pxx_to_hypervisor()
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/linux-4.1.27/include/xen/interface/ |
H A D | platform.h | 406 struct xen_pct_register control_register; member in struct:xen_processor_performance
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