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Searched refs:clock_ctl (Results 1 – 3 of 3) sorted by relevance

/linux-4.1.27/arch/mips/ath25/
Dar2315.c206 static unsigned __init ar2315_sys_clk(u32 clock_ctl) in ar2315_sys_clk() argument
220 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { in ar2315_sys_clk()
236 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); in ar2315_sys_clk()
/linux-4.1.27/drivers/memstick/host/
Djmb38x_ms.c686 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0; in jmb38x_ms_set_param() local
732 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param()
739 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param()
745 clock_ctl |= CLOCK_CONTROL_50MHZ; in jmb38x_ms_set_param()
752 writel(clock_ctl, host->addr + CLOCK_CONTROL); in jmb38x_ms_set_param()
/linux-4.1.27/drivers/net/ethernet/broadcom/
Dtg3.c6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write() local
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP); in tg3_refclk_write()
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME); in tg3_refclk_write()
6255 u32 clock_ctl; in tg3_ptp_enable() local
6264 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()
6265 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK; in tg3_ptp_enable()
6293 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0); in tg3_ptp_enable()
6296 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl); in tg3_ptp_enable()