| /linux-4.1.27/drivers/clk/ |
| H A D | clk-clps711x.c | 122 clk_register_divider_table(NULL, "timer1", "timer_ref", 0, _clps711x_clk_init()
126 clk_register_divider_table(NULL, "timer2", "timer_ref", 0, _clps711x_clk_init()
135 clk_register_divider_table(NULL, "spi", "spi_ref", 0, _clps711x_clk_init()
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| H A D | clk-divider.c | 486 * clk_register_divider_table - register a table based divider clock with
499 struct clk *clk_register_divider_table(struct device *dev, const char *name, clk_register_divider_table() function
508 EXPORT_SYMBOL_GPL(clk_register_divider_table); variable
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| /linux-4.1.27/drivers/clk/sunxi/ |
| H A D | clk-sun6i-apb0.c | 51 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, sun6i_a31_apb0_clk_probe()
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| H A D | clk-sunxi.c | 879 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, sunxi_divider_clk_setup()
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| /linux-4.1.27/drivers/clk/shmobile/ |
| H A D | clk-r8a73a4.c | 186 return clk_register_divider_table(NULL, name, parent_name, 0, r8a73a4_cpg_register_clock()
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| H A D | clk-r8a7740.c | 141 return clk_register_divider_table(NULL, name, parent_name, 0, r8a7740_cpg_register_clock()
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| H A D | clk-sh73a0.c | 158 return clk_register_divider_table(NULL, name, parent_name, 0, sh73a0_cpg_register_clock()
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| H A D | clk-rcar-gen2.c | 362 return clk_register_divider_table(NULL, name, parent_name, 0, rcar_gen2_cpg_register_clock()
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| /linux-4.1.27/drivers/clk/tegra/ |
| H A D | clk-divider.c | 198 return clk_register_divider_table(NULL, name, parent_name, 0, reg, tegra_clk_register_mc()
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| H A D | clk-tegra114.c | 1152 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, tegra114_pll_init()
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| H A D | clk-tegra124.c | 1273 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, tegra124_pll_init()
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| /linux-4.1.27/drivers/clk/hisilicon/ |
| H A D | clk.c | 159 clk = clk_register_divider_table(NULL, clks[i].name, hisi_clk_register_divider()
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| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | clk-imx6sl.c | 265 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
267 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
268 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6sl_clocks_init()
269 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); imx6sl_clocks_init()
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| H A D | clk-imx6sx.c | 226 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, imx6sx_clocks_init()
229 clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, imx6sx_clocks_init()
255 clks[IMX6SX_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", imx6sx_clocks_init()
259 clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", imx6sx_clocks_init()
261 clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", imx6sx_clocks_init()
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| H A D | clk-imx6q.c | 215 clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, imx6q_clocks_init()
256 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
258 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
259 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6q_clocks_init()
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| H A D | clk-vf610.c | 232 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); vf610_clocks_init()
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| /linux-4.1.27/drivers/clk/rockchip/ |
| H A D | clk.c | 234 clk = clk_register_divider_table(NULL, rockchip_clk_register_branches()
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| /linux-4.1.27/drivers/clk/samsung/ |
| H A D | clk.c | 224 clk = clk_register_divider_table(NULL, list->name, samsung_clk_register_div()
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| /linux-4.1.27/drivers/clk/st/ |
| H A D | clkgen-mux.c | 516 clk = clk_register_divider_table(NULL, clk_name, parent_name, 0, st_of_clkgena_prediv_setup()
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| /linux-4.1.27/arch/powerpc/platforms/512x/ |
| H A D | clock-commonclk.c | 253 return clk_register_divider_table(NULL, name, parent_name, 0, mpc512x_clk_divtable()
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| /linux-4.1.27/include/linux/ |
| H A D | clk-provider.h | 379 struct clk *clk_register_divider_table(struct device *dev, const char *name,
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