| /linux-4.1.27/drivers/clk/shmobile/ |
| D | clk-div6.c | 47 val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
59 val = clk_readl(clock->reg); in cpg_div6_clock_disable()
76 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
83 unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; in cpg_div6_clock_recalc_rate()
117 val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK; in cpg_div6_clock_set_rate()
134 hw_index = (clk_readl(clock->reg) >> clock->src_shift) & in cpg_div6_clock_get_parent()
158 clk_writel((clk_readl(clock->reg) & mask) | in cpg_div6_clock_set_parent()
215 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; in cpg_div6_clock_init()
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| D | clk-r8a73a4.c | 74 u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR); in r8a73a4_cpg_register_clock()
98 u32 value = clk_readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
105 u32 value = clk_readl(cpg->reg + CPG_PLL1CR); in r8a73a4_cpg_register_clock()
128 value = clk_readl(cpg->reg + cr); in r8a73a4_cpg_register_clock()
164 mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift) in r8a73a4_cpg_register_clock()
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| D | clk-r8a7740.c | 101 u32 value = clk_readl(cpg->reg + CPG_FRQCRC); in r8a7740_cpg_register_clock()
105 u32 value = clk_readl(cpg->reg + CPG_FRQCRA); in r8a7740_cpg_register_clock()
110 u32 value = clk_readl(cpg->reg + CPG_PLLC2CR); in r8a7740_cpg_register_clock()
114 u32 value = clk_readl(cpg->reg + CPG_USBCKCR); in r8a7740_cpg_register_clock()
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| D | clk-sh73a0.c | 88 u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
113 if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
114 mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
117 if (clk_readl(enable_reg) & BIT(20)) in sh73a0_cpg_register_clock()
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| D | clk-rcar-gen2.c | 64 val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) in cpg_z_clk_recalc_rate()
97 if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) in cpg_z_clk_set_rate()
100 val = clk_readl(zclk->reg); in cpg_z_clk_set_rate()
109 kick = clk_readl(zclk->kick_reg); in cpg_z_clk_set_rate()
123 if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) in cpg_z_clk_set_rate()
320 u32 value = clk_readl(cpg->reg + CPG_PLL0CR); in rcar_gen2_cpg_register_clock()
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| D | clk-mstp.c | 67 value = clk_readl(group->smstpcr); in cpg_mstp_clock_endisable()
80 if (!(clk_readl(group->mstpsr) & bitmask)) in cpg_mstp_clock_endisable()
111 value = clk_readl(group->mstpsr); in cpg_mstp_clock_is_enabled()
113 value = clk_readl(group->smstpcr); in cpg_mstp_clock_is_enabled()
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| D | clk-rz.c | 57 val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3; in rz_cpg_register_clock()
59 val = clk_readl(cpg->reg + CPG_FRQCR2) & 3; in rz_cpg_register_clock()
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| /linux-4.1.27/drivers/clk/zynq/ |
| D | pll.c | 93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
115 reg = clk_readl(clk->pll_ctrl); in zynq_pll_is_enabled()
141 reg = clk_readl(clk->pll_ctrl); in zynq_pll_enable()
144 while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit))) in zynq_pll_enable()
171 reg = clk_readl(clk->pll_ctrl); in zynq_pll_disable()
226 reg = clk_readl(pll->pll_ctrl); in clk_register_zynq_pll()
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| D | clkc.c | 153 enable_reg = clk_readl(fclk_gate_reg) & 1; in zynq_clk_register_fclk()
283 tmp = clk_readl(SLCR_621_TRUE) & 1; in zynq_clk_setup()
506 tmp = clk_readl(SLCR_DBG_CLK_CTRL); in zynq_clk_setup()
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| /linux-4.1.27/drivers/clk/ti/ |
| D | apll.c | 55 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
60 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_enable()
68 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
99 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_disable()
113 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_is_enabled()
232 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_is_enabled()
258 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_enable()
264 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in omap2_apll_enable()
288 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_disable()
306 v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg); in omap2_apll_set_autoidle()
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| D | autoidle.c | 41 val = ti_clk_ll_ops->clk_readl(clk->reg); in ti_allow_autoidle()
55 val = ti_clk_ll_ops->clk_readl(clk->reg); in ti_deny_autoidle()
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| D | mux.c | 44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
90 val = ti_clk_ll_ops->clk_readl(mux->reg); in ti_clk_mux_set_parent()
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| D | divider.c | 105 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
237 val = ti_clk_ll_ops->clk_readl(divider->reg); in ti_clk_divider_set_rate()
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| D | gate.c | 81 orig_v = ti_clk_ll_ops->clk_readl(parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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| /linux-4.1.27/drivers/clk/ |
| D | clk-gate.c | 61 reg = clk_readl(gate->reg); in clk_gate_endisable()
92 reg = clk_readl(gate->reg); in clk_gate_is_enabled()
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| D | clk-fractional-divider.c | 31 val = clk_readl(fd->reg); in clk_fd_recalc_rate()
84 val = clk_readl(fd->reg); in clk_fd_set_rate()
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| D | clk-mux.c | 45 val = clk_readl(mux->reg) >> mux->shift; in clk_mux_get_parent()
92 val = clk_readl(mux->reg); in clk_mux_set_parent()
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| D | clk-divider.c | 140 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate()
396 val = clk_readl(divider->reg); in clk_divider_set_rate()
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| /linux-4.1.27/include/linux/ |
| D | clk-provider.h | 668 static inline u32 clk_readl(u32 __iomem *reg) in clk_readl() function
680 static inline u32 clk_readl(u32 __iomem *reg) in clk_readl() function
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| /linux-4.1.27/include/linux/clk/ |
| D | ti.h | 251 u32 (*clk_readl)(void __iomem *reg); member
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| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | clock.c | 128 .clk_readl = clk_memmap_readl,
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| /linux-4.1.27/drivers/clk/tegra/ |
| D | clk-tegra124.c | 1496 plld_base = clk_readl(clk_base + PLLD_BASE); in tegra124_132_clock_init_pre()
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