Searched refs:clk_pll2 (Results 1 – 4 of 4) sorted by relevance
| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| D | clock.c | 86 static struct clk clk_pll2 = { variable
90 .parent = &clk_pll2,
214 INIT_CK(NULL, "pll2", &clk_pll2),
362 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()
380 mclk = &clk_pll2; in calc_clk_div()
537 clk_pll2.rate = clk_xtali.rate; in ep93xx_clock_init()
539 clk_pll2.rate = calc_pll_rate(value); in ep93xx_clock_init()
541 clk_pll2.rate = 0; in ep93xx_clock_init()
544 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); in ep93xx_clock_init()
555 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); in ep93xx_clock_init()
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| /linux-4.1.27/drivers/clk/sirf/ |
| D | clk-common.c | 223 static struct clk_pll clk_pll2 = { variable
413 if (rate == clk_get_rate(clk_pll2.hw.clk)) { in cpu_clk_set_rate()
414 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); in cpu_clk_set_rate()
427 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); in cpu_clk_set_rate()
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| D | clk-prima2.c | 73 &clk_pll2.hw,
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| D | clk-atlas6.c | 74 &clk_pll2.hw,
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