Searched refs:clk_pll1 (Results 1 – 4 of 4) sorted by relevance
| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| D | clock.c | 74 static struct clk clk_pll1 = { variable
78 .parent = &clk_pll1,
81 .parent = &clk_pll1,
84 .parent = &clk_pll1,
210 INIT_CK(NULL, "pll1", &clk_pll1),
362 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()
378 mclk = &clk_pll1; in calc_clk_div()
524 clk_pll1.rate = clk_xtali.rate; in ep93xx_clock_init()
526 clk_pll1.rate = calc_pll_rate(value); in ep93xx_clock_init()
529 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; in ep93xx_clock_init()
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| /linux-4.1.27/drivers/clk/sirf/ |
| D | clk-common.c | 216 static struct clk_pll clk_pll1 = { variable
408 if (rate == clk_get_rate(clk_pll1.hw.clk)) { in cpu_clk_set_rate()
409 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
426 if (cur_parent == clk_pll1.hw.clk) { in cpu_clk_set_rate()
431 ret2 = clk_set_rate(clk_pll1.hw.clk, rate); in cpu_clk_set_rate()
433 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
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| D | clk-prima2.c | 72 &clk_pll1.hw,
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| D | clk-atlas6.c | 73 &clk_pll1.hw,
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