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Searched refs:channel_writel (Results 1 – 6 of 6) sorted by relevance

/linux-4.1.27/drivers/dma/dw/
Dcore.c142 channel_writel(dwc, CFG_LO, cfglo); in dwc_initialize()
143 channel_writel(dwc, CFG_HI, cfghi); in dwc_initialize()
202 channel_writel(dwc, SAR, desc->lli.sar); in dwc_do_single_block()
203 channel_writel(dwc, DAR, desc->lli.dar); in dwc_do_single_block()
204 channel_writel(dwc, CTL_LO, ctllo); in dwc_do_single_block()
205 channel_writel(dwc, CTL_HI, desc->lli.ctlhi); in dwc_do_single_block()
251 channel_writel(dwc, LLP, first->txd.phys); in dwc_dostart()
252 channel_writel(dwc, CTL_LO, in dwc_dostart()
254 channel_writel(dwc, CTL_HI, 0); in dwc_dostart()
565 channel_writel(dwc, LLP, 0); in dwc_handle_cyclic()
[all …]
Dregs.h267 #define channel_writel(dwc, name, val) \ macro
/linux-4.1.27/drivers/dma/
Dpch_dma.c124 #define channel_writel(pdc, name, val) \ macro
349 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr); in pdc_dostart()
350 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr); in pdc_dostart()
351 channel_writel(pd_chan, SIZE, desc->regs.size); in pdc_dostart()
352 channel_writel(pd_chan, NEXT, desc->regs.next); in pdc_dostart()
355 channel_writel(pd_chan, NEXT, desc->txd.phys); in pdc_dostart()
792 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr); in pch_dma_restore_regs()
793 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr); in pch_dma_restore_regs()
794 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size); in pch_dma_restore_regs()
795 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next); in pch_dma_restore_regs()
Dtxx9dmac.c57 #define channel_writel(dc, name, val) \ macro
316 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
322 channel_writel(dc, CHAR, 0); in txx9dmac_reset_chan()
323 channel_writel(dc, SAR, 0); in txx9dmac_reset_chan()
324 channel_writel(dc, DAR, 0); in txx9dmac_reset_chan()
326 channel_writel(dc, CNTR, 0); in txx9dmac_reset_chan()
327 channel_writel(dc, SAIR, 0); in txx9dmac_reset_chan()
328 channel_writel(dc, DAIR, 0); in txx9dmac_reset_chan()
329 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
526 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
Dat_hdmac.c245 channel_writel(atchan, SADDR, 0); in atc_dostart()
246 channel_writel(atchan, DADDR, 0); in atc_dostart()
247 channel_writel(atchan, CTRLA, 0); in atc_dostart()
248 channel_writel(atchan, CTRLB, 0); in atc_dostart()
249 channel_writel(atchan, DSCR, first->txd.phys); in atc_dostart()
1411 channel_writel(atchan, CFG, cfg); in atc_alloc_chan_resources()
1891 channel_writel(atchan, SADDR, 0); in atc_resume_cyclic()
1892 channel_writel(atchan, DADDR, 0); in atc_resume_cyclic()
1893 channel_writel(atchan, CTRLA, 0); in atc_resume_cyclic()
1894 channel_writel(atchan, CTRLB, 0); in atc_resume_cyclic()
[all …]
Dat_hdmac_regs.h268 #define channel_writel(atchan, name, val) \ macro