Searched refs:carl9170_regwrite (Results 1 - 3 of 3) sorted by relevance

/linux-4.1.27/drivers/net/wireless/ath/carl9170/
H A Dmac.c129 carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, basic); carl9170_set_mac_rates()
130 carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, mandatory); carl9170_set_mac_rates()
140 carl9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min | carl9170_set_qos()
142 carl9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min | carl9170_set_qos()
144 carl9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min | carl9170_set_qos()
146 carl9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min | carl9170_set_qos()
148 carl9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min | carl9170_set_qos()
151 carl9170_regwrite(AR9170_MAC_REG_AC2_AC1_AC0_AIFS, carl9170_set_qos()
155 carl9170_regwrite(AR9170_MAC_REG_AC4_AC3_AC2_AIFS, carl9170_set_qos()
160 carl9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP, carl9170_set_qos()
162 carl9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP, carl9170_set_qos()
176 carl9170_regwrite(0x1c3600, 0x3); carl9170_init_mac()
178 carl9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40); carl9170_init_mac()
180 carl9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0x0); carl9170_init_mac()
182 carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER, carl9170_init_mac()
186 carl9170_regwrite(AR9170_MAC_REG_SNIFFER, carl9170_init_mac()
189 carl9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80); carl9170_init_mac()
191 carl9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70); carl9170_init_mac()
192 carl9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000); carl9170_init_mac()
193 carl9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10); carl9170_init_mac()
196 carl9170_regwrite(AR9170_MAC_REG_TID_CFACK_CFEND_RATE, 0x59900000); carl9170_init_mac()
199 carl9170_regwrite(AR9170_MAC_REG_TXOP_DURATION, 0x201); carl9170_init_mac()
203 carl9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170); carl9170_init_mac()
205 carl9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105); carl9170_init_mac()
208 carl9170_regwrite(AR9170_MAC_REG_AMPDU_FACTOR, 0x8000a); carl9170_init_mac()
209 carl9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, 0x140a07); carl9170_init_mac()
211 carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER, carl9170_init_mac()
214 carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL, carl9170_init_mac()
219 carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f); carl9170_init_mac()
220 carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f); carl9170_init_mac()
221 carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x0030033); carl9170_init_mac()
224 carl9170_regwrite(AR9170_MAC_REG_ACK_TPC, 0x4003c1e); carl9170_init_mac()
226 carl9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff); carl9170_init_mac()
229 carl9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008); carl9170_init_mac()
232 carl9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0); carl9170_init_mac()
235 carl9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011); carl9170_init_mac()
237 carl9170_regwrite(AR9170_MAC_REG_FCS_SELECT, carl9170_init_mac()
241 carl9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND, carl9170_init_mac()
245 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, 0xffffffff); carl9170_init_mac()
246 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, 0xffffffff); carl9170_init_mac()
249 carl9170_regwrite(AR9170_MAC_REG_PRETBTT, 0x0); carl9170_init_mac()
250 carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, 0x0); carl9170_init_mac()
267 carl9170_regwrite(reg, get_unaligned_le32(mac)); carl9170_set_mac_reg()
268 carl9170_regwrite(reg + 4, get_unaligned_le16(mac + 4)); carl9170_set_mac_reg()
290 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, mc_hash >> 32); carl9170_update_multicast()
291 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, mc_hash); carl9170_update_multicast()
387 carl9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer); carl9170_set_operating_mode()
388 carl9170_regwrite(AR9170_MAC_REG_CAM_MODE, cam_mode); carl9170_set_operating_mode()
389 carl9170_regwrite(AR9170_MAC_REG_ENCRYPTION, enc_mode); carl9170_set_operating_mode()
390 carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL, rx_ctrl); carl9170_set_operating_mode()
468 carl9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt); carl9170_set_beacon_timers()
469 carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v); carl9170_set_beacon_timers()
528 carl9170_regwrite(AR9170_MAC_REG_ACK_TPC, carl9170_set_mac_tpc()
530 carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC, carl9170_set_mac_tpc()
533 carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC, carl9170_set_mac_tpc()
H A Dphy.c48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); carl9170_init_power_cal()
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); carl9170_init_power_cal()
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); carl9170_init_power_cal()
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); carl9170_init_power_cal()
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); carl9170_init_power_cal()
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); carl9170_init_power_cal()
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); carl9170_init_power_cal()
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); carl9170_init_power_cal()
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); carl9170_init_power_cal()
57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); carl9170_init_power_cal()
446 carl9170_regwrite(AR9170_PHY_REG_SWITCH_COM, carl9170_init_phy_from_eeprom()
450 carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_0, carl9170_init_phy_from_eeprom()
454 carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_2, carl9170_init_phy_from_eeprom()
462 carl9170_regwrite(AR9170_PHY_REG_SETTLING, val); carl9170_init_phy_from_eeprom()
469 carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val); carl9170_init_phy_from_eeprom()
477 carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val); carl9170_init_phy_from_eeprom()
482 carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val); carl9170_init_phy_from_eeprom()
487 carl9170_regwrite(0x1c8864, val); carl9170_init_phy_from_eeprom()
492 carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val); carl9170_init_phy_from_eeprom()
498 carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val); carl9170_init_phy_from_eeprom()
506 carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val); carl9170_init_phy_from_eeprom()
512 carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val); carl9170_init_phy_from_eeprom()
519 carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val); carl9170_init_phy_from_eeprom()
526 carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val); carl9170_init_phy_from_eeprom()
534 carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val); carl9170_init_phy_from_eeprom()
536 carl9170_regwrite(AR9170_PHY_REG_RX_CHAINMASK, ar->eeprom.rx_mask); carl9170_init_phy_from_eeprom()
537 carl9170_regwrite(AR9170_PHY_REG_CAL_CHAINMASK, ar->eeprom.rx_mask); carl9170_init_phy_from_eeprom()
565 carl9170_regwrite(ar5416_phy_init[i].reg, val); carl9170_init_phy()
679 carl9170_regwrite(carl9170_rf_initval[i].reg, carl9170_init_rf_banks_0_7()
1023 carl9170_regwrite(0x1c58b0, fd0); carl9170_init_rf_bank4_pwr()
1024 carl9170_regwrite(0x1c58e8, fd1); carl9170_init_rf_bank4_pwr()
1202 carl9170_regwrite(0x1c6280 + chain * 0x1000 + carl9170_set_freq_cal_data()
1209 carl9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2), carl9170_set_freq_cal_data()
H A Dcmd.h87 #define carl9170_regwrite(r, v) do { \ macro

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