| /linux-4.1.27/arch/mn10300/mm/ |
| D | cache-inv-by-tag.S | 187 beq mn10300_local_dcache_inv_range_skip_0 # jump if this cacheline
192 bne mn10300_local_dcache_inv_range_skip_0 # jump if not this cacheline
201 beq mn10300_local_dcache_inv_range_skip_1 # jump if this cacheline
206 bne mn10300_local_dcache_inv_range_skip_1 # jump if not this cacheline
215 beq mn10300_local_dcache_inv_range_skip_2 # jump if this cacheline
220 bne mn10300_local_dcache_inv_range_skip_2 # jump if not this cacheline
229 beq mn10300_local_dcache_inv_range_skip_3 # jump if this cacheline
234 bne mn10300_local_dcache_inv_range_skip_3 # jump if not this cacheline
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| D | cache-dbg-inv-by-reg.S | 26 # Invalidate one particular cacheline if it's in the icache
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| D | Kconfig.cache | 12 the affected cacheline to be read into the cache first before being
14 is filled and a cacheline needs to be displaced from the cache to
19 cacheline is also in cache, it will be updated too.
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| D | cache-dbg-inv-by-tag.S | 28 # Invalidate one particular cacheline if it's in the icache
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| D | cache-dbg-flush-by-tag.S | 94 # round cacheline addr down
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| D | cache-dbg-flush-by-reg.S | 94 # Invalidate one particular cacheline if it's in the icache
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| /linux-4.1.27/include/asm-generic/ |
| D | vmlinux.lds.h | 712 #define PERCPU_INPUT(cacheline) \ argument
717 . = ALIGN(cacheline); \
719 . = ALIGN(cacheline); \
748 #define PERCPU_VADDR(cacheline, vaddr, phdr) \ argument
752 PERCPU_INPUT(cacheline) \
768 #define PERCPU_SECTION(cacheline) \ argument
772 PERCPU_INPUT(cacheline) \
794 #define RW_DATA_SECTION(cacheline, pagealigned, inittask) \ argument
800 CACHELINE_ALIGNED_DATA(cacheline) \
801 READ_MOSTLY_DATA(cacheline) \
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| /linux-4.1.27/drivers/md/bcache/ |
| D | bset.c | 503 static struct bkey *cacheline_to_bkey(struct bset_tree *t, unsigned cacheline, in cacheline_to_bkey() argument
506 return ((void *) t->data) + cacheline * BSET_CACHELINE + offset * 8; in cacheline_to_bkey()
515 unsigned cacheline, in bkey_to_cacheline_offset() argument
518 return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); in bkey_to_cacheline_offset()
535 static struct bkey *table_to_bkey(struct bset_tree *t, unsigned cacheline) in table_to_bkey() argument
537 return cacheline_to_bkey(t, cacheline, t->prev[cacheline]); in table_to_bkey()
638 unsigned j, cacheline = 1; in bch_bset_build_written_tree() local
659 while (bkey_to_cacheline(t, k) < cacheline) in bch_bset_build_written_tree()
663 t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); in bch_bset_build_written_tree()
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| /linux-4.1.27/arch/frv/ |
| D | Kconfig | 163 the affected cacheline to be read into the cache first before being
165 is filled and a cacheline needs to be displaced from the cache to
169 write won't fetch a cacheline into the cache if there isn't already
174 cacheline is also in cache, it will be updated too.
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| /linux-4.1.27/kernel/ |
| D | Kconfig.hz | 13 contention and cacheline bounces as a result of timer interrupts.
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| /linux-4.1.27/arch/frv/kernel/ |
| D | head-mmu-fr451.S | 43 # GR5 - cacheline size
64 setlos #32,gr5 ; cacheline size
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| D | head-uc-fr401.S | 42 # GR5 - cacheline size
63 setlos #32,gr5 ; cacheline size
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| D | head-uc-fr555.S | 41 # GR5 - cacheline size
62 setlos #64,gr5 ; cacheline size
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| D | sleep.S | 126 # - we want it to be be cacheline aligned so we can lock it into the icache easily
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| /linux-4.1.27/arch/sparc/kernel/ |
| D | prom_irqtrans.c | 354 static unsigned char cacheline[64] in tomatillo_wsync_handler() local
365 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
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| D | cherrs.S | 202 sub %g1, %g2, %g1 ! Move down 1 cacheline
214 subcc %g1, %g2, %g1 ! Next cacheline
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| /linux-4.1.27/arch/parisc/kernel/ |
| D | perf_asm.S | 145 ; Cacheline start (32-byte cacheline)
158 ; Cacheline start (32-byte cacheline)
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| /linux-4.1.27/Documentation/locking/ |
| D | mutex-design.txt | 66 cacheline bouncing that common test-and-set spinlock implementations
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| /linux-4.1.27/drivers/edac/ |
| D | Kconfig | 126 - inject_section (0..3, 16-byte section of 64-byte cacheline),
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| /linux-4.1.27/tools/perf/Documentation/ |
| D | perf-report.txt | 136 - dcacheline: the cacheline the data address is on at the time of sample
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| /linux-4.1.27/Documentation/ |
| D | DMA-API-HOWTO.txt | 134 buffers were cacheline-aligned. Without that, you'd see cacheline
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| D | memory-barriers.txt | 2674 cacheline over to the accessing CPU and propagate the effects upon conflict.
2739 displace a dirty cacheline or to do a speculative load;
2773 cacheline holding p may get updated in one of the second CPU's caches whilst
2774 the update to the cacheline holding v is delayed in the other of the second
2843 obscure the fact that RAM has been updated, until at such time as the cacheline
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| /linux-4.1.27/drivers/scsi/aic7xxx/ |
| D | aic7xxx.seq | 754 * We fetch a "cacheline aligned" and sized amount of data
758 * cacheline size is unknown.
795 * If the ending address is on a cacheline boundary,
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| D | aic7xxx.reg | 1436 * Partial transfer past cacheline end to be
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| D | aic79xx.seq | 1523 * We fetch a "cacheline aligned" and sized amount of data
1527 * cacheline size is unknown.
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| /linux-4.1.27/Documentation/filesystems/ |
| D | path-lookup.txt | 32 common path elements causes lock and cacheline queueing.
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| /linux-4.1.27/drivers/char/ |
| D | Kconfig | 178 of threads across a large system which avoids bouncing a cacheline
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| /linux-4.1.27/Documentation/cgroups/ |
| D | memory.txt | 562 to avoid unnecessary cacheline false sharing. usage_in_bytes is affected by the
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