Searched refs:cached_irq_mask (Results 1 - 18 of 18) sorted by relevance

/linux-4.1.27/drivers/irqchip/
H A Dirq-xtensa-pic.c22 unsigned int cached_irq_mask; variable
47 cached_irq_mask &= ~(1 << d->hwirq); xtensa_irq_mask()
48 set_sr(cached_irq_mask, intenable); xtensa_irq_mask()
53 cached_irq_mask |= 1 << d->hwirq; xtensa_irq_unmask()
54 set_sr(cached_irq_mask, intenable); xtensa_irq_unmask()
H A Dirq-xtensa-mx.c24 static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
62 __this_cpu_write(cached_irq_mask, secondary_init_irq()
78 mask = __this_cpu_read(cached_irq_mask) & ~mask; xtensa_mx_irq_mask()
79 __this_cpu_write(cached_irq_mask, mask); xtensa_mx_irq_mask()
93 mask |= __this_cpu_read(cached_irq_mask); xtensa_mx_irq_unmask()
94 __this_cpu_write(cached_irq_mask, mask); xtensa_mx_irq_unmask()
/linux-4.1.27/arch/alpha/kernel/
H A Dirq_pyxis.c21 static unsigned long cached_irq_mask; variable
34 pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); pyxis_enable_irq()
40 pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); pyxis_disable_irq()
47 unsigned long mask = cached_irq_mask &= ~bit; pyxis_mask_and_ack_irq()
74 pld &= cached_irq_mask; pyxis_device_interrupt()
H A Dirq_i8259.c23 static unsigned int cached_irq_mask = 0xffff; variable
39 i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); i8259a_enable_irq()
46 i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq); __i8259a_disable_irq()
H A Dsys_rx164.c35 static unsigned long cached_irq_mask; variable
51 rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); rx164_enable_irq()
57 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); rx164_disable_irq()
H A Dsys_dp264.c40 static unsigned long cached_irq_mask; variable
103 cached_irq_mask |= 1UL << d->irq; dp264_enable_irq()
104 tsunami_update_irq_hw(cached_irq_mask); dp264_enable_irq()
112 cached_irq_mask &= ~(1UL << d->irq); dp264_disable_irq()
113 tsunami_update_irq_hw(cached_irq_mask); dp264_disable_irq()
121 cached_irq_mask |= 1UL << (d->irq - 16); clipper_enable_irq()
122 tsunami_update_irq_hw(cached_irq_mask); clipper_enable_irq()
130 cached_irq_mask &= ~(1UL << (d->irq - 16)); clipper_disable_irq()
131 tsunami_update_irq_hw(cached_irq_mask); clipper_disable_irq()
156 tsunami_update_irq_hw(cached_irq_mask); dp264_set_affinity()
168 tsunami_update_irq_hw(cached_irq_mask); clipper_set_affinity()
H A Dsys_wildfire.c32 static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)]; variable
59 *enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano]; wildfire_update_irq_hw()
114 set_bit(irq, &cached_irq_mask); wildfire_enable_irq()
128 clear_bit(irq, &cached_irq_mask); wildfire_disable_irq()
142 clear_bit(irq, &cached_irq_mask); wildfire_mask_and_ack_irq()
H A Dsys_eb64p.c37 static unsigned int cached_irq_mask = -1; variable
48 eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); eb64p_enable_irq()
54 eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq); eb64p_disable_irq()
H A Dsys_eiger.c40 static unsigned long cached_irq_mask[2] = { -1, -1 }; variable
57 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); eiger_enable_irq()
66 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); eiger_disable_irq()
H A Dsys_mikasa.c37 static int cached_irq_mask; variable
48 mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16)); mikasa_enable_irq()
54 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16))); mikasa_disable_irq()
H A Dsys_alcor.c36 static unsigned long cached_irq_mask; variable
48 alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); alcor_enable_irq()
54 alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); alcor_disable_irq()
H A Dsys_noritake.c37 static int cached_irq_mask; variable
53 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); noritake_enable_irq()
59 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); noritake_disable_irq()
H A Dsys_takara.c34 static unsigned long cached_irq_mask[2] = { -1, -1 }; variable
51 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); takara_enable_irq()
60 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); takara_disable_irq()
H A Dsys_cabriolet.c38 static unsigned long cached_irq_mask = ~0UL; variable
50 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); cabriolet_enable_irq()
56 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); cabriolet_disable_irq()
/linux-4.1.27/arch/x86/include/asm/
H A Di8259.h6 extern unsigned int cached_irq_mask;
9 #define cached_master_mask (__byte(0, cached_irq_mask))
10 #define cached_slave_mask (__byte(1, cached_irq_mask))
/linux-4.1.27/arch/mips/kernel/
H A Di8259.c55 static unsigned int cached_irq_mask = 0xffff; variable
57 #define cached_master_mask (cached_irq_mask)
58 #define cached_slave_mask (cached_irq_mask >> 8)
67 cached_irq_mask |= mask; disable_8259A_irq()
82 cached_irq_mask &= mask; enable_8259A_irq()
166 if (cached_irq_mask & irqmask) mask_and_ack_8259A()
168 cached_irq_mask |= irqmask; mask_and_ack_8259A()
/linux-4.1.27/arch/x86/kernel/
H A Di8259.c43 unsigned int cached_irq_mask = 0xffff; variable
62 cached_irq_mask |= mask; mask_8259A_irq()
81 cached_irq_mask &= mask; unmask_8259A_irq()
169 if (cached_irq_mask & irqmask) mask_and_ack_8259A()
171 cached_irq_mask |= irqmask; mask_and_ack_8259A()
/linux-4.1.27/arch/powerpc/kernel/
H A Dirq.c25 * and complement of the cached_irq_mask. I want to be able to stuff

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