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/linux-4.1.27/arch/s390/include/asm/
H A Dcss_chars.h8 u32 dynio : 1; /* bit 12 */
10 u32 eadm : 1; /* bit 17 */
12 u32 aif : 1; /* bit 41 */
14 u32 mcss : 1; /* bit 45 */
15 u32 fcs : 1; /* bit 46 */
17 u32 ext_mb : 1; /* bit 48 */
19 u32 aif_tdd : 1; /* bit 56 */
21 u32 qebsm : 1; /* bit 58 */
23 u32 aif_osa : 1; /* bit 67 */
25 u32 eadm_rf : 1; /* bit 80 */
27 u32 cib : 1; /* bit 82 */
29 u32 fcx : 1; /* bit 88 */
31 u32 alt_ssi : 1; /* bit 108 */
33 u32 narf:1; /* bit 110 */
H A Dairq.h28 /* Adapter interrupt bit vector */
30 unsigned long *vector; /* Adapter interrupt bit vector */
31 unsigned long *avail; /* Allocation bit mask for the bit vector */
32 unsigned long *bitlock; /* Lock bit mask for the bit vector */
33 unsigned long *ptr; /* Pointer associated with each bit */
34 unsigned int *data; /* 32 bit value associated with each bit */
36 unsigned long end; /* Number of highest allocated bit + 1 */
40 #define AIRQ_IV_ALLOC 1 /* Use an allocation bit mask */
41 #define AIRQ_IV_BITLOCK 2 /* Allocate the lock bit mask */
48 void airq_iv_free(struct airq_iv *iv, unsigned long bit, unsigned long num);
57 static inline void airq_iv_free_bit(struct airq_iv *iv, unsigned long bit) airq_iv_free_bit() argument
59 airq_iv_free(iv, bit, 1); airq_iv_free_bit()
67 static inline void airq_iv_lock(struct airq_iv *iv, unsigned long bit) airq_iv_lock() argument
70 bit_spin_lock(bit ^ be_to_le, iv->bitlock); airq_iv_lock()
73 static inline void airq_iv_unlock(struct airq_iv *iv, unsigned long bit) airq_iv_unlock() argument
76 bit_spin_unlock(bit ^ be_to_le, iv->bitlock); airq_iv_unlock()
79 static inline void airq_iv_set_data(struct airq_iv *iv, unsigned long bit, airq_iv_set_data() argument
82 iv->data[bit] = data; airq_iv_set_data()
86 unsigned long bit) airq_iv_get_data()
88 return iv->data[bit]; airq_iv_get_data()
91 static inline void airq_iv_set_ptr(struct airq_iv *iv, unsigned long bit, airq_iv_set_ptr() argument
94 iv->ptr[bit] = ptr; airq_iv_set_ptr()
98 unsigned long bit) airq_iv_get_ptr()
100 return iv->ptr[bit]; airq_iv_get_ptr()
85 airq_iv_get_data(struct airq_iv *iv, unsigned long bit) airq_iv_get_data() argument
97 airq_iv_get_ptr(struct airq_iv *iv, unsigned long bit) airq_iv_get_ptr() argument
H A Dctl_reg.h31 static inline void __ctl_set_bit(unsigned int cr, unsigned int bit) __ctl_set_bit() argument
36 reg |= 1UL << bit; __ctl_set_bit()
40 static inline void __ctl_clear_bit(unsigned int cr, unsigned int bit) __ctl_clear_bit() argument
45 reg &= ~(1UL << bit); __ctl_clear_bit()
49 void smp_ctl_set_bit(int cr, int bit);
50 void smp_ctl_clear_bit(int cr, int bit);
68 # define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
69 # define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
71 # define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
72 # define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
H A Delf.h12 #define R_390_8 1 /* Direct 8 bit. */
13 #define R_390_12 2 /* Direct 12 bit. */
14 #define R_390_16 3 /* Direct 16 bit. */
15 #define R_390_32 4 /* Direct 32 bit. */
16 #define R_390_PC32 5 /* PC relative 32 bit. */
17 #define R_390_GOT12 6 /* 12 bit GOT offset. */
18 #define R_390_GOT32 7 /* 32 bit GOT offset. */
19 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
24 #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */
25 #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
26 #define R_390_GOT16 15 /* 16 bit GOT offset. */
27 #define R_390_PC16 16 /* PC relative 16 bit. */
28 #define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */
29 #define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */
30 #define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */
31 #define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */
32 #define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */
33 #define R_390_64 22 /* Direct 64 bit. */
34 #define R_390_PC64 23 /* PC relative 64 bit. */
35 #define R_390_GOT64 24 /* 64 bit GOT offset. */
36 #define R_390_PLT64 25 /* 64 bit PC relative PLT address. */
37 #define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */
38 #define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */
39 #define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */
40 #define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */
41 #define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */
42 #define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */
43 #define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */
44 #define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */
45 #define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */
46 #define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */
47 #define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */
53 #define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic
55 #define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic
57 #define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS
59 #define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS
61 #define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS
63 #define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic
65 #define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic
67 #define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for
69 #define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for
71 #define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for
73 #define R_390_TLS_LE32 50 /* 32 bit negated offset relative to
75 #define R_390_TLS_LE64 51 /* 64 bit negated offset relative to
77 #define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS
79 #define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS
85 #define R_390_20 57 /* Direct 20 bit. */
86 #define R_390_GOT20 58 /* 20 bit GOT offset. */
87 #define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */
88 #define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS
160 that it will "exec", and that there is sufficient room for the brk. 64-bit
H A Dbitops.h12 * bit depends on the word size.
21 * bitmaps, these work on similar bit arrays layouts, but
25 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
26 * number field needs to be reversed compared to the big-endian bit
35 * The main difference is that bit 0-63 (64b) or 0-31 (32b) in the bit
36 * number field needs to be reversed compared to the LSB0 encoded bit
280 * Functions which use MSB0 bit numbering.
322 * Returns the bit number of the most significant bit set,
323 * where the most significant bit has bit number 0.
324 * If no bit is set this function returns 64.
329 unsigned long bit = 0; __flogr() local
335 bit += 32; __flogr()
339 bit += 16; __flogr()
343 bit += 8; __flogr()
347 bit += 4; __flogr()
351 bit += 2; __flogr()
355 bit += 1; __flogr()
357 return bit; __flogr()
359 register unsigned long bit asm("4") = word; __flogr()
363 " flogr %[bit],%[bit]\n" __flogr()
364 : [bit] "+d" (bit), [out] "=d" (out) : : "cc"); __flogr()
365 return bit; __flogr()
370 * __ffs - find first bit in word.
373 * Undefined if no bit exists, so code should check against 0 first.
381 * ffs - find first bit set
396 * __fls - find last (most-significant) set bit in a long word
399 * Undefined if no set bit exists, so code should check against 0 first.
407 * fls64 - find last set bit in a 64-bit word
411 * ffsll, but returns the position of the most significant set bit.
414 * set bit if value is nonzero. The last (most significant) bit is
425 * fls - find last (most-significant) bit set
/linux-4.1.27/drivers/mtd/nand/
H A Dnand_ids.c34 {"TC58NVG2S0F 4G 3.3V 8-bit",
37 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 {"TC58NVG5D2 32G 3.3V 8-bit",
43 {"TC58NVG6D2 64G 3.3V 8-bit",
46 {"SDTNRGAMA 64G 3.3V 8-bit",
49 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
55 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
56 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
57 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
58 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
60 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
61 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
62 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
63 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
65 LEGACY_ID_NAND("NAND 32MiB 1,8V 8-bit", 0x35, 32, SZ_16K, SP_OPTIONS),
66 LEGACY_ID_NAND("NAND 32MiB 3,3V 8-bit", 0x75, 32, SZ_16K, SP_OPTIONS),
67 LEGACY_ID_NAND("NAND 32MiB 1,8V 16-bit", 0x45, 32, SZ_16K, SP_OPTIONS16),
68 LEGACY_ID_NAND("NAND 32MiB 3,3V 16-bit", 0x55, 32, SZ_16K, SP_OPTIONS16),
70 LEGACY_ID_NAND("NAND 64MiB 1,8V 8-bit", 0x36, 64, SZ_16K, SP_OPTIONS),
71 LEGACY_ID_NAND("NAND 64MiB 3,3V 8-bit", 0x76, 64, SZ_16K, SP_OPTIONS),
72 LEGACY_ID_NAND("NAND 64MiB 1,8V 16-bit", 0x46, 64, SZ_16K, SP_OPTIONS16),
73 LEGACY_ID_NAND("NAND 64MiB 3,3V 16-bit", 0x56, 64, SZ_16K, SP_OPTIONS16),
75 LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x78, 128, SZ_16K, SP_OPTIONS),
76 LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x39, 128, SZ_16K, SP_OPTIONS),
77 LEGACY_ID_NAND("NAND 128MiB 3,3V 8-bit", 0x79, 128, SZ_16K, SP_OPTIONS),
78 LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x72, 128, SZ_16K, SP_OPTIONS16),
79 LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x49, 128, SZ_16K, SP_OPTIONS16),
80 LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x74, 128, SZ_16K, SP_OPTIONS16),
81 LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x59, 128, SZ_16K, SP_OPTIONS16),
83 LEGACY_ID_NAND("NAND 256MiB 3,3V 8-bit", 0x71, 256, SZ_16K, SP_OPTIONS),
91 EXTENDED_ID_NAND("NAND 64MiB 1,8V 8-bit", 0xA2, 64, LP_OPTIONS),
92 EXTENDED_ID_NAND("NAND 64MiB 1,8V 8-bit", 0xA0, 64, LP_OPTIONS),
93 EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xF2, 64, LP_OPTIONS),
94 EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xD0, 64, LP_OPTIONS),
95 EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xF0, 64, LP_OPTIONS),
96 EXTENDED_ID_NAND("NAND 64MiB 1,8V 16-bit", 0xB2, 64, LP_OPTIONS16),
97 EXTENDED_ID_NAND("NAND 64MiB 1,8V 16-bit", 0xB0, 64, LP_OPTIONS16),
98 EXTENDED_ID_NAND("NAND 64MiB 3,3V 16-bit", 0xC2, 64, LP_OPTIONS16),
99 EXTENDED_ID_NAND("NAND 64MiB 3,3V 16-bit", 0xC0, 64, LP_OPTIONS16),
102 EXTENDED_ID_NAND("NAND 128MiB 1,8V 8-bit", 0xA1, 128, LP_OPTIONS),
103 EXTENDED_ID_NAND("NAND 128MiB 3,3V 8-bit", 0xF1, 128, LP_OPTIONS),
104 EXTENDED_ID_NAND("NAND 128MiB 3,3V 8-bit", 0xD1, 128, LP_OPTIONS),
105 EXTENDED_ID_NAND("NAND 128MiB 1,8V 16-bit", 0xB1, 128, LP_OPTIONS16),
106 EXTENDED_ID_NAND("NAND 128MiB 3,3V 16-bit", 0xC1, 128, LP_OPTIONS16),
107 EXTENDED_ID_NAND("NAND 128MiB 1,8V 16-bit", 0xAD, 128, LP_OPTIONS16),
110 EXTENDED_ID_NAND("NAND 256MiB 1,8V 8-bit", 0xAA, 256, LP_OPTIONS),
111 EXTENDED_ID_NAND("NAND 256MiB 3,3V 8-bit", 0xDA, 256, LP_OPTIONS),
112 EXTENDED_ID_NAND("NAND 256MiB 1,8V 16-bit", 0xBA, 256, LP_OPTIONS16),
113 EXTENDED_ID_NAND("NAND 256MiB 3,3V 16-bit", 0xCA, 256, LP_OPTIONS16),
116 EXTENDED_ID_NAND("NAND 512MiB 1,8V 8-bit", 0xAC, 512, LP_OPTIONS),
117 EXTENDED_ID_NAND("NAND 512MiB 3,3V 8-bit", 0xDC, 512, LP_OPTIONS),
118 EXTENDED_ID_NAND("NAND 512MiB 1,8V 16-bit", 0xBC, 512, LP_OPTIONS16),
119 EXTENDED_ID_NAND("NAND 512MiB 3,3V 16-bit", 0xCC, 512, LP_OPTIONS16),
122 EXTENDED_ID_NAND("NAND 1GiB 1,8V 8-bit", 0xA3, 1024, LP_OPTIONS),
123 EXTENDED_ID_NAND("NAND 1GiB 3,3V 8-bit", 0xD3, 1024, LP_OPTIONS),
124 EXTENDED_ID_NAND("NAND 1GiB 1,8V 16-bit", 0xB3, 1024, LP_OPTIONS16),
125 EXTENDED_ID_NAND("NAND 1GiB 3,3V 16-bit", 0xC3, 1024, LP_OPTIONS16),
128 EXTENDED_ID_NAND("NAND 2GiB 1,8V 8-bit", 0xA5, 2048, LP_OPTIONS),
129 EXTENDED_ID_NAND("NAND 2GiB 3,3V 8-bit", 0xD5, 2048, LP_OPTIONS),
130 EXTENDED_ID_NAND("NAND 2GiB 1,8V 16-bit", 0xB5, 2048, LP_OPTIONS16),
131 EXTENDED_ID_NAND("NAND 2GiB 3,3V 16-bit", 0xC5, 2048, LP_OPTIONS16),
134 EXTENDED_ID_NAND("NAND 4GiB 1,8V 8-bit", 0xA7, 4096, LP_OPTIONS),
135 EXTENDED_ID_NAND("NAND 4GiB 3,3V 8-bit", 0xD7, 4096, LP_OPTIONS),
136 EXTENDED_ID_NAND("NAND 4GiB 1,8V 16-bit", 0xB7, 4096, LP_OPTIONS16),
137 EXTENDED_ID_NAND("NAND 4GiB 3,3V 16-bit", 0xC7, 4096, LP_OPTIONS16),
140 EXTENDED_ID_NAND("NAND 8GiB 1,8V 8-bit", 0xAE, 8192, LP_OPTIONS),
141 EXTENDED_ID_NAND("NAND 8GiB 3,3V 8-bit", 0xDE, 8192, LP_OPTIONS),
142 EXTENDED_ID_NAND("NAND 8GiB 1,8V 16-bit", 0xBE, 8192, LP_OPTIONS16),
143 EXTENDED_ID_NAND("NAND 8GiB 3,3V 16-bit", 0xCE, 8192, LP_OPTIONS16),
146 EXTENDED_ID_NAND("NAND 16GiB 1,8V 8-bit", 0x1A, 16384, LP_OPTIONS),
147 EXTENDED_ID_NAND("NAND 16GiB 3,3V 8-bit", 0x3A, 16384, LP_OPTIONS),
148 EXTENDED_ID_NAND("NAND 16GiB 1,8V 16-bit", 0x2A, 16384, LP_OPTIONS16),
149 EXTENDED_ID_NAND("NAND 16GiB 3,3V 16-bit", 0x4A, 16384, LP_OPTIONS16),
152 EXTENDED_ID_NAND("NAND 32GiB 1,8V 8-bit", 0x1C, 32768, LP_OPTIONS),
153 EXTENDED_ID_NAND("NAND 32GiB 3,3V 8-bit", 0x3C, 32768, LP_OPTIONS),
154 EXTENDED_ID_NAND("NAND 32GiB 1,8V 16-bit", 0x2C, 32768, LP_OPTIONS16),
155 EXTENDED_ID_NAND("NAND 32GiB 3,3V 16-bit", 0x4C, 32768, LP_OPTIONS16),
158 EXTENDED_ID_NAND("NAND 64GiB 1,8V 8-bit", 0x1E, 65536, LP_OPTIONS),
159 EXTENDED_ID_NAND("NAND 64GiB 3,3V 8-bit", 0x3E, 65536, LP_OPTIONS),
160 EXTENDED_ID_NAND("NAND 64GiB 1,8V 16-bit", 0x2E, 65536, LP_OPTIONS16),
161 EXTENDED_ID_NAND("NAND 64GiB 3,3V 16-bit", 0x4E, 65536, LP_OPTIONS16),
/linux-4.1.27/arch/m68k/include/asm/
H A Dmac_baboon.h12 * bit 5 : slot 2 power control
13 * bit 6 : slot 1 power control
18 * bit 0: ????
19 * bit 1: IDE interrupt active?
20 * bit 2: bay status, 0 = full, 1 = empty
21 * bit 3: ????
26 * bit 0: ????
27 * bit 1: IDE controller interrupt
28 * bit 2: media bay status change interrupt
H A Dintersil.h9 /* bit 2 */
13 /* bit 3 */
17 /* bit 4 */
21 /* bit 5 */
H A Dmac_psc.h111 * [ 16-bit ]
114 * bit 0 : ????
115 * bit 1 : ????
116 * bit 2 : Set to one to enable sound
118 * bit 3 : ????
119 * bit 4 : ????
120 * bit 5 : ????
121 * bit 6 : Set to one to enable pass-thru
125 * bit 7 : Set to one to activate the
128 * bit 8 : Set to one to activate the
131 * bit 9 : \
132 * bit 11 : |
152 * [ 32-bit ]
166 * [ 32-bit ]
171 * [ 16-bit ]
172 * Unknown 16-bit value, always 0x0000.
175 * [ 16-bit ]
181 * channels are 1 bit wide.
184 * [ 32-bit ]
188 * [ 32-bit ]
192 * [ 16-bit ]
196 * [ 16-bit ]
200 * [ 16-bit ]
205 * [ 16-bit ]
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_sgdmahw.h33 /* bit 0: error
34 * bit 1: length error
35 * bit 2: crc error
36 * bit 3: truncated error
37 * bit 4: phy error
38 * bit 5: collision error
39 * bit 6: reserved
40 * bit 7: status eop for recv case
44 /* bit 0: eop
45 * bit 1: read_fixed
46 * bit 2: write fixed
48 * bit 7: hardware owned
72 /* bit 0: error
73 * bit 1: eop
74 * bit 2: descriptor completed
75 * bit 3: chain completed
76 * bit 4: busy
82 /* bit 0: interrupt on error
83 * bit 1: interrupt on eop
84 * bit 2: interrupt after every descriptor
85 * bit 3: interrupt after last descrip in a chain
86 * bit 4: global interrupt enable
87 * bit 5: starts descriptor processing
88 * bit 6: stop core on dma error
89 * bit 7: interrupt on max descriptors
91 * bit 16: Software reset
92 * bit 17: clears owned by hardware if 0, does not clear otherwise
93 * bit 18: enables descriptor polling mode
94 * bit 19-26: clocks before polling again
95 * bit 27-30: reserved
96 * bit 31: clear interrupt
H A Daltera_msgdmahw.h28 u32 burst_seq_num; /* bit 31:24 write burst
29 * bit 23:16 read burst
30 * bit 15:0 sequence number
32 u32 stride; /* bit 31:16 write stride
33 * bit 15:0 read stride
40 /* mSGDMA descriptor control field bit definitions
53 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
91 u32 rw_fill_level; /* bit 31:16 - write fill level
92 * bit 15:0 - read fill level
94 u32 resp_fill_level; /* bit 15:0 */
95 u32 rw_seq_num; /* bit 31:16 - write sequence number
96 * bit 15:0 - read sequence number
101 /* mSGDMA CSR status register bit definitions
127 /* mSGDMA CSR control register bit definitions
153 /* mSGDMA response register bit definitions
/linux-4.1.27/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h52 * bit 0.. 9 : lifetime_expiry_value:10
53 * bit 10 : interrupt_en:1
54 * bit 11 : status_en:1
55 * bit 12..13 : txss_override:2
56 * bit 14 : timestamp_insertion:1
57 * bit 15 : duration_preserve:1
58 * bit 16..21 : reserved0:6
59 * bit 22..26 : mcs_index:5
60 * bit 27 : mcs_en:1
61 * bit 28..30 : reserved1:3
62 * bit 31 : sn_preserved:1
64 * bit 0.. 3 : pkt_mode:4
65 * bit 4 : pkt_mode_en:1
66 * bit 5..14 : reserved0:10
67 * bit 15 : ack_policy_en:1
68 * bit 16..19 : dst_index:4
69 * bit 20 : dst_index_en:1
70 * bit 21..22 : ack_policy:2
71 * bit 23 : lifetime_en:1
72 * bit 24..30 : max_retry:7
73 * bit 31 : max_retry_en:1
75 * bit 0.. 7 : num_of_descriptors:8
76 * bit 8..17 : reserved:10
77 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11
78 * bit 20 : snap_hdr_insertion_en:1
79 * bit 21 : vlan_removal_en:1
80 * bit 22..31 : reserved0:10
82 * bit 0.. 31: ucode_cmd:32
246 * bit 0.. 7 : l4_length:8 layer 4 length
247 * bit 8 : cmd_eop:1 This descriptor is the last one in the packet
248 * bit 9 : reserved
249 * bit 10 : cmd_dma_it:1 immediate interrupt
250 * bit 11..12 : SBD - Segment Buffer Details
255 * bit 13 : TSE - TCP Segmentation Enable
256 * bit 14 : IIC - Directs the HW to Insert IPv4 Checksum
257 * bit 15 : ITC - Directs the HW to Insert TCP/UDP Checksum
258 * bit 16..20 : QID - The target QID that the packet should be stored
260 * bit 21 : PO - Pseudo header Offload:
263 * bit 22 : NC - No UDP Checksum
264 * bit 23..29 : reserved
265 * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved
268 * bit 0..31 : addr_low:32 The payload buffer low address
270 * bit 0..15 : addr_high:16 The payload buffer high address
271 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum
273 * bit 24..30 : mac_length:7
274 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
277 * bit 0 2 : mac_status:3
278 * bit 3 7 : reserved:5
280 * bit 0 : DU:1 Descriptor Used
281 * bit 1 7 : reserved:7
296 * bit 0.. 3 : tid:4 The QoS (b3-0) TID Field
297 * bit 4.. 6 : cid:3 The Source index that was found during parsing the TA.
299 * bit 7 : reserved:1
300 * bit 8.. 9 : mid:2 The MAC virtual number
301 * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type
303 * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype
304 * bit 16..27 : seq_number:12 The received Sequence number field
305 * bit 28..31 : extended:4 extended subtype
307 * bit 0.. 3 : reserved
308 * bit 4.. 5 : key_id:2
309 * bit 6 : decrypt_bypass:1
310 * bit 7 : security:1 FC (b14)
311 * bit 8.. 9 : ds_bits:2 FC (b9-8)
312 * bit 10 : a_msdu_present:1 QoS (b7)
313 * bit 11 : a_msdu_type:1 QoS (b8)
314 * bit 12 : a_mpdu:1 part of AMPDU aggregation
315 * bit 13 : broadcast:1
316 * bit 14 : mutlicast:1
317 * bit 15 : reserved:1
318 * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
320 * bit 21..24 : mcs:4
321 * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt
323 * bit 29..31 : reserved:3
325 * bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received
326 * bit 3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version
327 * bit 5 : fc_order:1 The FC Control (b15) -Order
328 * bit 6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field
329 * bit 8 : esop:1 The QoS (b4) ESOP field
330 * bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
331 * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
332 * bit 15 : qos_ac_constraint:1 QoS (b15)
333 * bit 16..31 : pn_15_0:16 low 2 bytes of PN
335 * bit 0..31 : pn_47_16:32 high 4 bytes of PN
347 * bit 0.. 7 : l4_length:8 layer 4 length. The field is only valid if
348 * L4I bit is set
349 * bit 8 : cmd_eop:1 set to 1
350 * bit 9 : cmd_rt:1 set to 1
351 * bit 10 : cmd_dma_it:1 immediate interrupt
352 * bit 11..15 : reserved:5
353 * bit 16..29 : phy_info_length:14 It is valid when the PII is set.
354 * When the FFM bit is set bits 29-27 are used for for
357 * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
360 * bit 0..31 : addr_low:32 The payload buffer low address
362 * bit 0..15 : addr_high:16 The payload buffer high address
363 * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set
364 * bit 24..30 : mac_length:7
365 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
368 * bit 0 : FCS:1
369 * bit 1 : MIC:1
370 * bit 2 : Key miss:1
371 * bit 3 : Replay:1
372 * bit 4 : L3:1 IPv4 checksum
373 * bit 5 : L4:1 TCP/UDP checksum
374 * bit 6 7 : reserved:2
376 * bit 0 : DU:1 Descriptor Used
377 * bit 1 : EOP:1 The descriptor indicates the End of Packet
378 * bit 2 : error:1
379 * bit 3 : MI:1 MAC Interrupt is asserted (according to parser decision)
380 * bit 4 : L3I:1 L3 identified and checksum calculated
381 * bit 5 : L4I:1 L4 identified and checksum calculated
382 * bit 6 : PII:1 PHY Info Included in the packet
383 * bit 7 : FFM:1 EtherType Flex Filter Match
/linux-4.1.27/drivers/media/platform/coda/
H A DMakefile3 coda-objs := coda-common.o coda-bit.o coda-h264.o coda-jpeg.o
/linux-4.1.27/include/uapi/linux/netfilter/
H A Dxt_connlabel.h10 __u16 bit; member in struct:xt_connlabel_mtinfo
H A Dnf_conntrack_tuple_common.h33 __be16 key; /* GRE key is 32bit, PPtP only uses 16bit */
/linux-4.1.27/arch/nios2/include/asm/
H A Dasm-macros.h3 * Some of the bit test macro can simplify down to one line
84 * the bit to make sure it is valid 32 value.
89 .macro BT reg1, reg2, bit
90 .if \bit > 31
93 .if \bit < 16
94 andi \reg1, \reg2, (1 << \bit)
96 andhi \reg1, \reg2, (1 << (\bit - 16))
102 * Tests the bit in reg2 and branches to label if the
103 * bit is zero. The result of the bit test is stored in reg1.
108 .macro BTBZ reg1, reg2, bit, label
109 BT \reg1, \reg2, \bit
114 * Tests the bit in reg2 and branches to label if the
115 * bit is non-zero. The result of the bit test is stored in reg1.
120 .macro BTBNZ reg1, reg2, bit, label
121 BT \reg1, \reg2, \bit
126 * Tests the bit in reg2 and then compliments the bit in reg2.
127 * The result of the bit test is stored in reg1.
132 .macro BTC reg1, reg2, bit
133 .if \bit > 31
136 .if \bit < 16
137 andi \reg1, \reg2, (1 << \bit)
138 xori \reg2, \reg2, (1 << \bit)
140 andhi \reg1, \reg2, (1 << (\bit - 16))
141 xorhi \reg2, \reg2, (1 << (\bit - 16))
147 * Tests the bit in reg2 and then sets the bit in reg2.
148 * The result of the bit test is stored in reg1.
153 .macro BTS reg1, reg2, bit
154 .if \bit > 31
157 .if \bit < 16
158 andi \reg1, \reg2, (1 << \bit)
159 ori \reg2, \reg2, (1 << \bit)
161 andhi \reg1, \reg2, (1 << (\bit - 16))
162 orhi \reg2, \reg2, (1 << (\bit - 16))
168 * Tests the bit in reg2 and then resets the bit in reg2.
169 * The result of the bit test is stored in reg1.
174 .macro BTR reg1, reg2, bit
175 .if \bit > 31
178 .if \bit < 16
179 andi \reg1, \reg2, (1 << \bit)
180 andi \reg2, \reg2, %lo(~(1 << \bit))
182 andhi \reg1, \reg2, (1 << (\bit - 16))
183 andhi \reg2, \reg2, %lo(~(1 << (\bit - 16)))
189 * Tests the bit in reg2 and then compliments the bit in reg2.
190 * The result of the bit test is stored in reg1. If the
191 * original bit was zero it branches to label.
196 .macro BTCBZ reg1, reg2, bit, label
197 BTC \reg1, \reg2, \bit
202 * Tests the bit in reg2 and then compliments the bit in reg2.
203 * The result of the bit test is stored in reg1. If the
204 * original bit was non-zero it branches to label.
209 .macro BTCBNZ reg1, reg2, bit, label
210 BTC \reg1, \reg2, \bit
215 * Tests the bit in reg2 and then sets the bit in reg2.
216 * The result of the bit test is stored in reg1. If the
217 * original bit was zero it branches to label.
222 .macro BTSBZ reg1, reg2, bit, label
223 BTS \reg1, \reg2, \bit
228 * Tests the bit in reg2 and then sets the bit in reg2.
229 * The result of the bit test is stored in reg1. If the
230 * original bit was non-zero it branches to label.
235 .macro BTSBNZ reg1, reg2, bit, label
236 BTS \reg1, \reg2, \bit
241 * Tests the bit in reg2 and then resets the bit in reg2.
242 * The result of the bit test is stored in reg1. If the
243 * original bit was zero it branches to label.
248 .macro BTRBZ reg1, reg2, bit, label
249 BTR \reg1, \reg2, \bit
254 * Tests the bit in reg2 and then resets the bit in reg2.
255 * The result of the bit test is stored in reg1. If the
256 * original bit was non-zero it branches to label.
261 .macro BTRBNZ reg1, reg2, bit, label
262 BTR \reg1, \reg2, \bit
/linux-4.1.27/include/uapi/linux/netfilter_bridge/
H A Debt_vlan.h16 __u8 bitmask; /* Args bitmask bit 1=1 - ID arg,
17 bit 2=1 User-Priority arg, bit 3=1 encap*/
18 __u8 invflags; /* Inverse bitmask bit 1=1 - inversed ID arg,
19 bit 2=1 - inversed Pirority arg */
/linux-4.1.27/arch/metag/include/asm/
H A Dbitops.h10 * These functions are the basis of our bit ops.
12 static inline void set_bit(unsigned int bit, volatile unsigned long *p) set_bit() argument
15 unsigned long mask = 1UL << (bit & 31); set_bit()
17 p += bit >> 5; set_bit()
25 static inline void clear_bit(unsigned int bit, volatile unsigned long *p) clear_bit() argument
28 unsigned long mask = 1UL << (bit & 31); clear_bit()
30 p += bit >> 5; clear_bit()
38 static inline void change_bit(unsigned int bit, volatile unsigned long *p) change_bit() argument
41 unsigned long mask = 1UL << (bit & 31); change_bit()
43 p += bit >> 5; change_bit()
51 static inline int test_and_set_bit(unsigned int bit, volatile unsigned long *p) test_and_set_bit() argument
55 unsigned long mask = 1UL << (bit & 31); test_and_set_bit()
57 p += bit >> 5; test_and_set_bit()
70 static inline int test_and_clear_bit(unsigned int bit, test_and_clear_bit() argument
75 unsigned long mask = 1UL << (bit & 31); test_and_clear_bit()
77 p += bit >> 5; test_and_clear_bit()
90 static inline int test_and_change_bit(unsigned int bit, test_and_change_bit() argument
95 unsigned long mask = 1UL << (bit & 31); test_and_change_bit()
97 p += bit >> 5; test_and_change_bit()
H A Dchecksum.h6 * and adds in "sum" (32-bit)
8 * returns a 32-bit number suitable for feeding into itself
14 * it's best to have buff aligned on a 32-bit boundary
22 * here even more important to align src and dst on a 32-bit (or even
23 * better 64-bit) boundary
31 * here even more important to align src and dst on a 32-bit (or even
32 * better 64-bit) boundary
59 * returns a 16-bit checksum, already complemented
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dbitfield.h10 * Purpose Definition of macros to operate on bit fields.
29 * The macro "Fld" encodes a bit field, given its size and its shift value
30 * with respect to bit 0.
33 * A more intuitive way to encode bit fields would have been to use their
34 * mask. However, extracting size and shift value information from a bit
39 * Size Size of the bit field, in number of bits.
40 * Shft Shift value of the bit field with respect to bit 0.
43 * Fld Encoded bit field.
54 * the size, shift value, mask, aligned mask, and first bit of a
55 * bit field.
58 * Field Encoded bit field (using the macro "Fld").
61 * FSize Size of the bit field, in number of bits.
62 * FShft Shift value of the bit field with respect to bit 0.
63 * FMsk Mask for the bit field.
64 * FAlnMsk Mask for the bit field, aligned on bit 0.
65 * F1stBit First bit of the bit field.
79 * The macro "FInsrt" inserts a value into a bit field by shifting the
84 * Field Encoded bit field (using the macro "Fld").
98 * The macro "FExtr" extracts the value of a bit field by masking and
102 * Data Data containing the bit-field to be extracted.
103 * Field Encoded bit field (using the macro "Fld").
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A Dbitfield.h10 * Purpose Definition of macros to operate on bit fields.
29 * The macro "Fld" encodes a bit field, given its size and its shift value
30 * with respect to bit 0.
33 * A more intuitive way to encode bit fields would have been to use their
34 * mask. However, extracting size and shift value information from a bit
39 * Size Size of the bit field, in number of bits.
40 * Shft Shift value of the bit field with respect to bit 0.
43 * Fld Encoded bit field.
54 * the size, shift value, mask, aligned mask, and first bit of a
55 * bit field.
58 * Field Encoded bit field (using the macro "Fld").
61 * FSize Size of the bit field, in number of bits.
62 * FShft Shift value of the bit field with respect to bit 0.
63 * FMsk Mask for the bit field.
64 * FAlnMsk Mask for the bit field, aligned on bit 0.
65 * F1stBit First bit of the bit field.
79 * The macro "FInsrt" inserts a value into a bit field by shifting the
84 * Field Encoded bit field (using the macro "Fld").
98 * The macro "FExtr" extracts the value of a bit field by masking and
102 * Data Data containing the bit-field to be extracted.
103 * Field Encoded bit field (using the macro "Fld").
/linux-4.1.27/security/selinux/ss/
H A Debitmap.h9 * an explicitly specified starting bit position within
66 unsigned int bit) ebitmap_next_positive()
70 ofs = find_next_bit((*n)->maps, EBITMAP_SIZE, bit - (*n)->startbit + 1); ebitmap_next_positive()
82 #define EBITMAP_NODE_INDEX(node, bit) \
83 (((bit) - (node)->startbit) / EBITMAP_UNIT_SIZE)
84 #define EBITMAP_NODE_OFFSET(node, bit) \
85 (((bit) - (node)->startbit) % EBITMAP_UNIT_SIZE)
88 unsigned int bit) ebitmap_node_get_bit()
90 unsigned int index = EBITMAP_NODE_INDEX(n, bit); ebitmap_node_get_bit()
91 unsigned int ofs = EBITMAP_NODE_OFFSET(n, bit); ebitmap_node_get_bit()
100 unsigned int bit) ebitmap_node_set_bit()
102 unsigned int index = EBITMAP_NODE_INDEX(n, bit); ebitmap_node_set_bit()
103 unsigned int ofs = EBITMAP_NODE_OFFSET(n, bit); ebitmap_node_set_bit()
110 unsigned int bit) ebitmap_node_clr_bit()
112 unsigned int index = EBITMAP_NODE_INDEX(n, bit); ebitmap_node_clr_bit()
113 unsigned int ofs = EBITMAP_NODE_OFFSET(n, bit); ebitmap_node_clr_bit()
119 #define ebitmap_for_each_positive_bit(e, n, bit) \
120 for (bit = ebitmap_start_positive(e, &n); \
121 bit < ebitmap_length(e); \
122 bit = ebitmap_next_positive(e, &n, bit)) \
127 int ebitmap_get_bit(struct ebitmap *e, unsigned long bit);
128 int ebitmap_set_bit(struct ebitmap *e, unsigned long bit, int value);
64 ebitmap_next_positive(struct ebitmap *e, struct ebitmap_node **n, unsigned int bit) ebitmap_next_positive() argument
87 ebitmap_node_get_bit(struct ebitmap_node *n, unsigned int bit) ebitmap_node_get_bit() argument
99 ebitmap_node_set_bit(struct ebitmap_node *n, unsigned int bit) ebitmap_node_set_bit() argument
109 ebitmap_node_clr_bit(struct ebitmap_node *n, unsigned int bit) ebitmap_node_clr_bit() argument
H A Debitmap.c15 * Applied standard bit operations to improve bitmap scanning.
195 * if last_e2bit is non-zero, the highest set bit in e2 cannot exceed
239 int ebitmap_get_bit(struct ebitmap *e, unsigned long bit) ebitmap_get_bit() argument
243 if (e->highbit < bit) ebitmap_get_bit()
247 while (n && (n->startbit <= bit)) { ebitmap_get_bit()
248 if ((n->startbit + EBITMAP_SIZE) > bit) ebitmap_get_bit()
249 return ebitmap_node_get_bit(n, bit); ebitmap_get_bit()
256 int ebitmap_set_bit(struct ebitmap *e, unsigned long bit, int value) ebitmap_set_bit() argument
262 while (n && n->startbit <= bit) { ebitmap_set_bit()
263 if ((n->startbit + EBITMAP_SIZE) > bit) { ebitmap_set_bit()
265 ebitmap_node_set_bit(n, bit); ebitmap_set_bit()
269 ebitmap_node_clr_bit(n, bit); ebitmap_set_bit()
306 new->startbit = bit - (bit % EBITMAP_SIZE); ebitmap_set_bit()
307 ebitmap_node_set_bit(new, bit); ebitmap_set_bit()
363 "match my size %Zd (high bit was %d)\n", ebitmap_read()
386 printk(KERN_ERR "SELinux: ebitmap start bit (%d) is " ebitmap_read()
392 printk(KERN_ERR "SELinux: ebitmap start bit (%d) is " ebitmap_read()
415 printk(KERN_ERR "SELinux: ebitmap: start bit %d" ebitmap_read()
416 " comes after start bit %d\n", ebitmap_read()
451 int bit, last_bit, last_startbit, rc; ebitmap_write() local
458 ebitmap_for_each_positive_bit(e, n, bit) { ebitmap_for_each_positive_bit()
459 if (rounddown(bit, (int)BITS_PER_U64) > last_startbit) { ebitmap_for_each_positive_bit()
461 last_startbit = rounddown(bit, BITS_PER_U64); ebitmap_for_each_positive_bit()
463 last_bit = roundup(bit + 1, BITS_PER_U64); ebitmap_for_each_positive_bit()
474 ebitmap_for_each_positive_bit(e, n, bit) { ebitmap_for_each_positive_bit()
475 if (rounddown(bit, (int)BITS_PER_U64) > last_startbit) { ebitmap_for_each_positive_bit()
478 /* this is the very first bit */ ebitmap_for_each_positive_bit()
480 last_startbit = rounddown(bit, BITS_PER_U64); ebitmap_for_each_positive_bit()
481 map = (u64)1 << (bit - last_startbit); ebitmap_for_each_positive_bit()
498 last_startbit = rounddown(bit, BITS_PER_U64); ebitmap_for_each_positive_bit()
500 map |= (u64)1 << (bit - last_startbit); ebitmap_for_each_positive_bit()
/linux-4.1.27/arch/x86/xen/
H A Dvdso.h2 bit 1 to avoid bugs in some versions of glibc when bit 0 is
/linux-4.1.27/arch/mips/include/asm/mach-au1x00/
H A Dau1550nd.h13 int devwidth; /* 0 = 8bit device, 1 = 16bit device */
/linux-4.1.27/include/linux/platform_data/
H A Dmax6697.h16 * For all bit masks:
17 * bit 0: local temperature
18 * bit 1..7: remote temperatures
24 u8 alert_mask; /* set bit to 1 to disable alert */
25 u8 over_temperature_mask; /* set bit to 1 to disable */
26 u8 resistance_cancellation; /* set bit to 0 to disable
27 * bit mask for MAX6581,
30 u8 ideality_mask; /* set bit to 0 to disable */
H A Dmtd-nand-omap2.h25 * 1-bit ECC: calculation and correction by SW
31 * 1-bit ECC: calculation by GPMC, Error detection by Software
35 /* 4-bit ECC calculation by GPMC, Error detection by Software */
37 /* 4-bit ECC calculation by GPMC, Error detection by ELM */
39 /* 8-bit ECC calculation by GPMC, Error detection by Software */
41 /* 8-bit ECC calculation by GPMC, Error detection by ELM */
43 /* 16-bit ECC calculation by GPMC, Error detection by ELM */
/linux-4.1.27/arch/alpha/include/uapi/asm/
H A Dstatfs.h6 /* Alpha is the only 64-bit platform with 32-bit statfs. And doesn't
H A Dauxvec.h13 bit 0-3: Cache set-associativity; 0 means fully associative.
14 bit 4-7: Log2 of cacheline size.
15 bit 8-31: Size of the entire cache >> 8.
16 bit 32-63: Reserved.
/linux-4.1.27/include/asm-generic/bitops/
H A Dbuiltin-__ffs.h5 * __ffs - find first bit in word.
8 * Undefined if no bit exists, so code should check against 0 first.
H A Dfind.h6 * find_next_bit - find the next set bit in a memory region
11 * Returns the bit number for the next set bit
20 * find_next_zero_bit - find the next cleared bit in a memory region
25 * Returns the bit number of the next zero bit
35 * find_first_bit - find the first set bit in a memory region
39 * Returns the bit number of the first set bit.
46 * find_first_zero_bit - find the first cleared bit in a memory region
50 * Returns the bit number of the first cleared bit.
H A Dfls64.h7 * fls64 - find last set bit in a 64-bit word
11 * ffsll, but returns the position of the most significant set bit.
14 * set bit if value is nonzero. The last (most significant) bit is
H A Dlock.h5 * test_and_set_bit_lock - Set a bit and return its old value, for lock
10 * It can be used to implement bit locks.
15 * clear_bit_unlock - Clear a bit in memory, for unlock
16 * @nr: the bit to set
28 * __clear_bit_unlock - Clear a bit in memory, for unlock
29 * @nr: the bit to set
H A Dbuiltin-__fls.h5 * __fls - find last (most-significant) set bit in a long word
8 * Undefined if no set bit exists, so code should check against 0 first.
H A Dbuiltin-fls.h5 * fls - find last (most-significant) bit set
H A D__ffs.h7 * __ffs - find first bit in word.
10 * Undefined if no bit exists, so code should check against 0 first.
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dipcbuf.h10 * - 32-bit seq
11 * - on sparc for 32 bit mode (it is 32 bit on sparc64)
12 * - 2 miscellaneous 64-bit values
H A Dpsrcompat.h6 /* Old 32-bit PSR fields for the compatibility conversion code. */
17 #define PSR_C 0x00100000 /* carry bit */
18 #define PSR_V 0x00200000 /* overflow bit */
19 #define PSR_Z 0x00400000 /* zero bit */
20 #define PSR_N 0x00800000 /* negative bit */
24 #define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
/linux-4.1.27/arch/microblaze/include/asm/
H A Dkgdb.h11 * 32 32-bit general purpose registers (r0-r31)
12 * 6 32-bit special registers (pc, msr, ear, esr, fsr, btr)
13 * 12 32-bit PVR
14 * 7 32-bit MMU Regs (redr, rpid, rzpr, rtlbx, rtlbsx, rtlblo, rtlbhi)
/linux-4.1.27/fs/omfs/
H A Dbitmap.c21 * Counts the run of zero bits starting at bit up to max.
26 int addrlen, int bit, int max) count_run()
32 x = find_next_bit(*addr, nbits, bit); count_run()
33 count += x - bit; count_run()
38 bit = 0; count_run()
44 * Sets or clears the run of count bits starting with bit.
48 int nbits, int bit, int count, int set) set_run()
60 for (i = 0; i < count; i++, bit++) { set_run()
61 if (bit >= nbits) { set_run()
62 bit = 0; set_run()
73 set_bit(bit, sbi->s_imap[map]); set_run()
74 set_bit(bit, (unsigned long *)bh->b_data); set_run()
76 clear_bit(bit, sbi->s_imap[map]); set_run()
77 clear_bit(bit, (unsigned long *)bh->b_data); set_run()
95 unsigned int map, bit; omfs_allocate_block() local
100 bit = do_div(tmp, bits_per_entry); omfs_allocate_block()
104 if (map >= sbi->s_imap_size || test_and_set_bit(bit, sbi->s_imap[map])) omfs_allocate_block()
112 set_bit(bit, (unsigned long *)bh->b_data); omfs_allocate_block()
138 int i, run, bit; omfs_allocate_range() local
142 bit = 0; omfs_allocate_range()
143 while (bit < bits_per_entry) { omfs_allocate_range()
144 bit = find_next_zero_bit(sbi->s_imap[i], bits_per_entry, omfs_allocate_range()
145 bit); omfs_allocate_range()
147 if (bit == bits_per_entry) omfs_allocate_range()
151 sbi->s_imap_size-i, bit, max_request); omfs_allocate_range()
155 bit += run; omfs_allocate_range()
162 *return_block = (u64) i * bits_per_entry + bit; omfs_allocate_range()
164 ret = set_run(sb, i, bits_per_entry, bit, run, 1); omfs_allocate_range()
179 unsigned int map, bit; omfs_clear_range() local
183 bit = do_div(tmp, bits_per_entry); omfs_clear_range()
190 ret = set_run(sb, map, bits_per_entry, bit, count, 0); omfs_clear_range()
25 count_run(unsigned long **addr, int nbits, int addrlen, int bit, int max) count_run() argument
47 set_run(struct super_block *sb, int map, int nbits, int bit, int count, int set) set_run() argument
/linux-4.1.27/arch/mn10300/include/asm/
H A Dbitops.h1 /* MN10300 bit operations
11 * These have to be done with inline assembly: that way the bit-setting
12 * is guaranteed to be atomic. All bit operations return 0 if the bit
15 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
24 * set bit
41 * clear bit
69 * test bit
77 * change bit
92 * test and set bit
113 * test and clear bit
134 * test and change bit
156 * __ffs - find first bit set
159 * - return 31..0 to indicate bit 31..0 most least significant bit set
165 int bit; __ffs() local
166 asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x) : "cc"); __ffs()
167 return bit; __ffs()
177 int bit; __ilog2_u32() local
178 asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n) : "cc"); __ilog2_u32()
179 return bit; __ilog2_u32()
183 * fls - find last bit set
187 * - return 32..1 to indicate bit 31..0 most significant bit set
197 * __fls - find last (most-significant) set bit in a long word
200 * Undefined if no set bit exists, so code should check against 0 first.
208 * ffs - find first bit set
211 * - return 32..1 to indicate bit 31..0 most least significant bit set
218 * (rightmost) 1-bit of the value in x. ffs()
/linux-4.1.27/arch/x86/vdso/vdso32/
H A Dvclock_gettime.c12 * in case of a 32 bit VDSO for a 64 bit kernel fake a 32 bit kernel
/linux-4.1.27/tools/include/linux/
H A Dbitops.h35 #define for_each_set_bit(bit, addr, size) \
36 for ((bit) = find_first_bit((addr), (size)); \
37 (bit) < (size); \
38 (bit) = find_next_bit((addr), (size), (bit) + 1))
40 /* same as for_each_set_bit() but use bit as value to start with */
41 #define for_each_set_bit_from(bit, addr, size) \
42 for ((bit) = find_next_bit((addr), (size), (bit)); \
43 (bit) < (size); \
44 (bit) = find_next_bit((addr), (size), (bit) + 1))
/linux-4.1.27/arch/x86/include/asm/
H A Dcpufeature.h15 #define NCAPINTS 13 /* N 32-bit words worth of info */
16 #define NBUGINTS 1 /* N 32-bit bug flags */
21 * this feature bit is not displayed in /proc/cpuinfo at all.
42 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
113 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
138 #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
159 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
160 #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
173 #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
222 #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
226 #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
291 #define test_cpu_cap(c, bit) \
292 test_bit(bit, (unsigned long *)((c)->x86_capability))
294 #define REQUIRED_MASK_BIT_SET(bit) \
295 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
296 (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
297 (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
298 (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \
299 (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
300 (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
301 (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
302 (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \
303 (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \
304 (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
306 #define DISABLED_MASK_BIT_SET(bit) \
307 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \
308 (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \
309 (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \
310 (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \
311 (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \
312 (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \
313 (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \
314 (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \
315 (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \
316 (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) )
318 #define cpu_has(c, bit) \
319 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
320 test_cpu_cap(c, bit))
322 #define this_cpu_has(bit) \
323 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
324 x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
334 #define cpu_feature_enabled(bit) \
335 (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \
336 cpu_has(&boot_cpu_data, bit))
338 #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
340 #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
341 #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
342 #define setup_clear_cpu_cap(bit) do { \
343 clear_cpu_cap(&boot_cpu_data, bit); \
344 set_bit(bit, (unsigned long *)cpu_caps_cleared); \
346 #define setup_force_cpu_cap(bit) do { \
347 set_cpu_cap(&boot_cpu_data, bit); \
348 set_bit(bit, (unsigned long *)cpu_caps_set); \
407 extern bool __static_cpu_has_safe(u16 bit);
414 static __always_inline __pure bool __static_cpu_has(u16 bit) __static_cpu_has() argument
444 " .word %P0\n" /* feature bit */ __static_cpu_has()
450 : : "i" (bit) : : t_no); __static_cpu_has()
470 " .word %P1\n" /* feature bit */ __static_cpu_has()
482 : "=qm" (flag) : "i" (bit)); __static_cpu_has()
488 #define static_cpu_has(bit) \
490 __builtin_constant_p(boot_cpu_has(bit)) ? \
491 boot_cpu_has(bit) : \
492 __builtin_constant_p(bit) ? \
493 __static_cpu_has(bit) : \
494 boot_cpu_has(bit) \
497 static __always_inline __pure bool _static_cpu_has_safe(u16 bit) _static_cpu_has_safe() argument
520 " .word %P0\n" /* feature bit */ _static_cpu_has_safe()
525 : : "i" (bit), "i" (X86_FEATURE_ALWAYS) _static_cpu_has_safe()
531 return __static_cpu_has_safe(bit); _static_cpu_has_safe()
555 " .word %P1\n" /* feature bit */ _static_cpu_has_safe()
568 : "i" (bit), "i" (X86_FEATURE_ALWAYS)); _static_cpu_has_safe()
569 return (flag == 2 ? __static_cpu_has_safe(bit) : flag); _static_cpu_has_safe()
573 #define static_cpu_has_safe(bit) \
575 __builtin_constant_p(boot_cpu_has(bit)) ? \
576 boot_cpu_has(bit) : \
577 _static_cpu_has_safe(bit) \
583 #define static_cpu_has(bit) boot_cpu_has(bit)
584 #define static_cpu_has_safe(bit) boot_cpu_has(bit)
587 #define cpu_has_bug(c, bit) cpu_has(c, (bit))
588 #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
589 #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit))
591 #define static_cpu_has_bug(bit) static_cpu_has((bit))
592 #define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit))
593 #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
H A Dsync_bitops.h9 * These have to be done with inline assembly: that way the bit-setting
10 * is guaranteed to be atomic. All bit operations return 0 if the bit
13 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
19 * sync_set_bit - Atomically set a bit in memory
20 * @nr: the bit to set
38 * sync_clear_bit - Clears a bit in memory
56 * sync_change_bit - Toggle a bit in memory
73 * sync_test_and_set_bit - Set a bit and return its old value
91 * sync_test_and_clear_bit - Clear a bit and return its old value
109 * sync_test_and_change_bit - Change a bit and return its old value
H A Dchecksum_64.h15 * csum_fold - Fold and invert a 32bit checksum.
16 * sum: 32bit unfolded sum
18 * Fold a 32bit running checksum to 16bit and invert it. This is usually
20 * Make sure not to mix with 64bit checksums.
81 * @sum: initial sum to be added in (32bit unfolded)
84 * 32bit unfolded.
107 * @sum: initial sum to be added in (32bit unfolded)
109 * Returns the 16bit pseudo header checksum the input data already
123 * @sum: initial sum to be added in (32bit unfolded)
125 * Returns the 32bit unfolded internet checksum of the buffer.
127 * buff should be aligned to a 64bit boundary if possible.
153 * ip_compute_csum - Compute an 16bit IP checksum.
157 * Returns the 16bit folded/inverted checksum of the passed buffer.
168 * @sum: initial sum (32bit unfolded) to be added in
172 * Returns the unfolded 32bit checksum.
H A Dbitops.h31 * These have to be done with inline assembly: that way the bit-setting
32 * is guaranteed to be atomic. All bit operations return 0 if the bit
35 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
57 * set_bit - Atomically set a bit in memory
58 * @nr: the bit to set
86 * __set_bit - Set a bit in memory
87 * @nr: the bit to set
100 * clear_bit - Clears a bit in memory
124 * clear_bit_unlock - Clears a bit in memory
143 * __clear_bit_unlock - Clears a bit in memory
161 * __change_bit - Toggle a bit in memory
162 * @nr: the bit to change
175 * change_bit - Toggle a bit in memory
197 * test_and_set_bit - Set a bit and return its old value
210 * test_and_set_bit_lock - Set a bit and return its old value for lock
223 * __test_and_set_bit - Set a bit and return its old value
243 * test_and_clear_bit - Clear a bit and return its old value
256 * __test_and_clear_bit - Clear a bit and return its old value
296 * test_and_change_bit - Change a bit and return its old value
328 * test_bit - Determine whether a bit is set
329 * @nr: bit number to test
341 * __ffs - find first set bit in word
344 * Undefined if no bit exists, so code should check against 0 first.
355 * ffz - find first zero bit in word
369 * __fls: find last set bit in word
372 * Undefined if no set bit exists, so code should check against 0 first.
386 * ffs - find first set bit in word
393 * set bit if value is nonzero. The first (least significant) bit
427 * fls - find last set bit in word
431 * ffs, but returns the position of the most significant set bit.
434 * set bit if value is nonzero. The last (most significant) bit is
468 * fls64 - find last set bit in a 64-bit word
472 * ffsll, but returns the position of the most significant set bit.
475 * set bit if value is nonzero. The last (most significant) bit is
/linux-4.1.27/include/linux/
H A Dbitops.h17 * Create a contiguous bitmask starting at bit position @l and ending at
19 * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
38 #define for_each_set_bit(bit, addr, size) \
39 for ((bit) = find_first_bit((addr), (size)); \
40 (bit) < (size); \
41 (bit) = find_next_bit((addr), (size), (bit) + 1))
43 /* same as for_each_set_bit() but use bit as value to start with */
44 #define for_each_set_bit_from(bit, addr, size) \
45 for ((bit) = find_next_bit((addr), (size), (bit)); \
46 (bit) < (size); \
47 (bit) = find_next_bit((addr), (size), (bit) + 1))
49 #define for_each_clear_bit(bit, addr, size) \
50 for ((bit) = find_first_zero_bit((addr), (size)); \
51 (bit) < (size); \
52 (bit) = find_next_zero_bit((addr), (size), (bit) + 1))
54 /* same as for_each_clear_bit() but use bit as value to start with */
55 #define for_each_clear_bit_from(bit, addr, size) \
56 for ((bit) = find_next_zero_bit((addr), (size), (bit)); \
57 (bit) < (size); \
58 (bit) = find_next_zero_bit((addr), (size), (bit) + 1))
84 * rol64 - rotate a 64-bit value left
94 * ror64 - rotate a 64-bit value right
104 * rol32 - rotate a 32-bit value left
114 * ror32 - rotate a 32-bit value right
124 * rol16 - rotate a 16-bit value left
134 * ror16 - rotate a 16-bit value right
144 * rol8 - rotate an 8-bit value left
154 * ror8 - rotate an 8-bit value right
164 * sign_extend32 - sign extend a 32-bit value using specified bit as sign-bit
166 * @index: 0 based bit index (0<=index<32) to sign bit
182 * __ffs64 - find first set bit in a 64 bit word
183 * @word: The 64 bit word
185 * On 64 bit arches this is a synomyn for __ffs
219 * find_last_bit - find the last set bit in a memory region
223 * Returns the bit number of the last set bit, or size.
H A Dexportfs.h31 * 32bit inode number, 32 bit generation number.
36 * 32bit inode number, 32 bit generation number,
37 * 32 bit parent directory inode number.
42 * 64 bit object ID, 64 bit root object ID,
43 * 32 bit generation number.
48 * 64 bit object ID, 64 bit root object ID,
49 * 32 bit generation number,
50 * 64 bit parent object ID, 32 bit parent generation.
55 * 64 bit object ID, 64 bit root object ID,
56 * 32 bit generation number,
57 * 64 bit parent object ID, 32 bit parent generation,
58 * 64 bit parent root object ID.
63 * 32 bit block number, 16 bit partition reference,
64 * 16 bit unused, 32 bit generation number.
69 * 32 bit block number, 16 bit partition reference,
70 * 16 bit unused, 32 bit generation number,
71 * 32 bit parent block number, 32 bit parent generation number
76 * 64 bit checkpoint number, 64 bit inode number,
77 * 32 bit generation number.
82 * 64 bit checkpoint number, 64 bit inode number,
83 * 32 bit generation number, 32 bit parent generation.
84 * 64 bit parent inode number.
89 * 32 bit generation number, 40 bit i_pos.
94 * 32 bit generation number, 40 bit i_pos,
95 * 32 bit parent generation number, 40 bit parent i_pos
H A Dmath64.h13 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
15 * This is commonly provided by 32bit archs to provide an optimized 64bit
25 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
43 * div64_u64 - unsigned 64bit divide with 64bit divisor
51 * div64_s64 - signed 64bit divide with 64bit divisor
90 * div_u64 - unsigned 64bit divide with 32bit divisor
92 * This is the most common 64bit divide and should be used if possible,
93 * as many 32bit archs can optimize this variant better than a full 64bit
105 * div_s64 - signed 64bit divide with 32bit divisor
H A Dnfs3.h10 /* Number of 32bit words in post_op_attr */
H A Deeprom_93xx46.h8 #define EE_ADDR8 0x01 /* 8 bit addr. cfg */
9 #define EE_ADDR16 0x02 /* 16 bit addr. cfg */
H A Dcciss_ioctl.h8 /* 32 bit compatible ioctl structs */
14 __u32 buf; /* 32 bit pointer to data buffer */
24 __u32 buf; /* 32 bit pointer to data buffer */
H A Dcnt32_to_63.h2 * Extend a 32-bit counter to 63 bits
34 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
39 * is a problem when implementing sched_clock() for example, where a 64-bit
42 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
44 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
46 * the top bit of both counters (hardware and in memory) differ then the
51 * always be in synch with the top bit indicating to any potential concurrent
59 * 32-bit counter;
62 * 32-bit counter half period minus the longest period between two
65 * Those requirements ensure proper update to the state bit in memory.
88 * Note that the top bit (bit 63) in the returned value should be considered
90 * multiplier on the returned value which can get rid of the top bit
92 * clear-bit instruction. Otherwise caller must remember to clear the top
93 * bit explicitly.
H A Ddtlk.h14 #define TTS_READABLE 0x80 /* mask for bit which is nonzero if a
16 #define TTS_SPEAKING 0x40 /* mask for SYNC bit, which is nonzero
21 #define TTS_SPEAKING2 0x20 /* mask for SYNC2 bit,
24 #define TTS_WRITABLE 0x10 /* mask for RDY bit, which when set to
27 bit goes zero 2-3 usec after
30 #define TTS_ALMOST_FULL 0x08 /* mask for AF bit: When set to 1,
35 #define TTS_ALMOST_EMPTY 0x04 /* mask for AE bit: When set to 1,
50 #define LPC_SPEAKING 0x80 /* mask for TS bit: When set to 1,
53 #define LPC_BUFFER_LOW 0x40 /* mask for BL bit: When set to 1,
58 #define LPC_BUFFER_EMPTY 0x20 /* mask for BE bit: When set to 1,
/linux-4.1.27/lib/
H A Ddiv64.c9 * Generic C version of 64bit/32bit division and modulo, with
10 * 64bit result and 32bit remainder.
23 /* Not needed on 64bit architectures */
33 /* Reduce the thing a bit first */ __div64_32()
82 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
83 * @dividend: 64bit dividend
84 * @divisor: 64bit divisor
85 * @remainder: 64bit remainder
89 * is kept distinct to avoid slowing down the div64_u64 operation on 32bit
122 * div64_u64 - unsigned 64bit divide with 64bit divisor
123 * @dividend: 64bit dividend
124 * @divisor: 64bit divisor
156 * div64_s64 - signed 64bit divide with 64bit divisor
157 * @dividend: 64bit dividend
158 * @divisor: 64bit divisor
H A Diomap_copy.c22 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
23 * @to: destination, in MMIO space (must be 32-bit aligned)
24 * @from: source (must be 32-bit aligned)
25 * @count: number of 32-bit quantities to copy
45 * __iowrite64_copy - copy data to MMIO space, in 64-bit or 32-bit units
46 * @to: destination, in MMIO space (must be 64-bit aligned)
47 * @from: source (must be 64-bit aligned)
48 * @count: number of 64-bit quantities to copy
/linux-4.1.27/drivers/memory/tegra/
H A Dtegra114.c29 .bit = 1,
43 .bit = 2,
57 .bit = 3,
71 .bit = 4,
85 .bit = 5,
99 .bit = 6,
113 .bit = 9,
127 .bit = 10,
141 .bit = 11,
155 .bit = 15,
169 .bit = 16,
183 .bit = 17,
197 .bit = 18,
211 .bit = 19,
225 .bit = 20,
239 .bit = 21,
253 .bit = 22,
267 .bit = 23,
281 .bit = 24,
295 .bit = 28,
309 .bit = 29,
323 .bit = 30,
337 .bit = 0,
351 .bit = 2,
365 .bit = 3,
379 .bit = 4,
393 .bit = 5,
427 .bit = 8,
441 .bit = 9,
455 .bit = 10,
469 .bit = 11,
483 .bit = 12,
497 .bit = 13,
511 .bit = 14,
525 .bit = 15,
539 .bit = 16,
553 .bit = 18,
567 .bit = 19,
581 .bit = 20,
595 .bit = 21,
609 .bit = 22,
623 .bit = 23,
657 .bit = 27,
671 .bit = 28,
685 .bit = 30,
699 .bit = 31,
713 .bit = 0,
727 .bit = 1,
741 .bit = 10,
755 .bit = 11,
769 .bit = 12,
783 .bit = 13,
797 .bit = 14,
811 .bit = 15,
825 .bit = 16,
839 .bit = 17,
873 .bit = 20,
887 .bit = 21,
H A Dtegra124.c29 .bit = 1,
43 .bit = 2,
57 .bit = 3,
71 .bit = 4,
85 .bit = 5,
99 .bit = 6,
113 .bit = 14,
127 .bit = 15,
141 .bit = 16,
155 .bit = 17,
169 .bit = 21,
183 .bit = 22,
197 .bit = 23,
211 .bit = 28,
225 .bit = 29,
239 .bit = 30,
253 .bit = 31,
267 .bit = 2,
281 .bit = 3,
295 .bit = 4,
309 .bit = 5,
343 .bit = 11,
357 .bit = 17,
371 .bit = 18,
385 .bit = 21,
399 .bit = 22,
433 .bit = 27,
447 .bit = 28,
461 .bit = 29,
475 .bit = 30,
489 .bit = 31,
503 .bit = 0,
517 .bit = 1,
531 .bit = 4,
545 .bit = 6,
559 .bit = 7,
573 .bit = 10,
587 .bit = 11,
601 .bit = 12,
615 .bit = 13,
629 .bit = 14,
643 .bit = 16,
657 .bit = 17,
671 .bit = 20,
685 .bit = 21,
699 .bit = 22,
713 .bit = 23,
728 .bit = 24,
743 .bit = 25,
757 .bit = 26,
771 .bit = 0,
785 .bit = 1,
799 .bit = 2,
813 .bit = 3,
827 .bit = 4,
841 .bit = 5,
855 .bit = 6,
869 .bit = 7,
883 .bit = 12,
897 .bit = 13,
911 .bit = 18,
925 .bit = 19,
H A Dtegra30.c29 .bit = 1,
43 .bit = 2,
57 .bit = 3,
71 .bit = 4,
85 .bit = 5,
99 .bit = 6,
113 .bit = 7,
127 .bit = 8,
141 .bit = 9,
155 .bit = 10,
169 .bit = 11,
183 .bit = 12,
197 .bit = 13,
211 .bit = 14,
225 .bit = 15,
239 .bit = 16,
253 .bit = 17,
267 .bit = 18,
281 .bit = 19,
295 .bit = 20,
309 .bit = 21,
323 .bit = 22,
337 .bit = 23,
351 .bit = 24,
365 .bit = 25,
379 .bit = 26,
393 .bit = 27,
407 .bit = 28,
421 .bit = 29,
435 .bit = 30,
449 .bit = 31,
463 .bit = 0,
477 .bit = 1,
491 .bit = 2,
505 .bit = 3,
519 .bit = 4,
533 .bit = 5,
567 .bit = 8,
581 .bit = 9,
595 .bit = 10,
609 .bit = 11,
623 .bit = 12,
637 .bit = 13,
651 .bit = 14,
665 .bit = 15,
679 .bit = 16,
693 .bit = 17,
707 .bit = 18,
721 .bit = 19,
735 .bit = 20,
749 .bit = 21,
763 .bit = 22,
777 .bit = 23,
811 .bit = 26,
825 .bit = 27,
839 .bit = 28,
853 .bit = 29,
867 .bit = 30,
881 .bit = 31,
895 .bit = 0,
909 .bit = 1,
/linux-4.1.27/drivers/net/ethernet/marvell/
H A Dskge.h136 /* B0_CTST 16 bit Control/Status register */
143 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
169 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
220 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
243 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
255 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
263 /* B2_CHIP_ID 8 bit Chip Identification Number */
277 /* B2_TI_CTRL 8 bit Timer control */
278 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
286 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
287 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
294 /* B2_GP_IO 32 bit General Purpose I/O Register */
323 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
331 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
343 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
349 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
354 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
361 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
366 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
376 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
392 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
415 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
416 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
417 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
418 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
422 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
439 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
440 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
441 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
442 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
443 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
444 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
445 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
464 Q_D = 0x00, /* 8*32 bit Current Descriptor */
465 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
466 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
467 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
468 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
469 Q_BC = 0x30, /* 32 bit Current Byte Counter */
470 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
471 Q_F = 0x38, /* 32 bit Flag Register */
472 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
473 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
474 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
475 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
476 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
477 Q_T2 = 0x40, /* 32 bit Test Register 2 */
478 Q_T3 = 0x44, /* 32 bit Test Register 3 */
486 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
487 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
488 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
489 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
490 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
491 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
492 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
493 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
495 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
496 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
497 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
498 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
499 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
541 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
542 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
544 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
545 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
546 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
547 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
548 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
549 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
550 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
551 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
552 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
554 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
555 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
556 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
557 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
559 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
560 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
561 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
562 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
563 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
567 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
586 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
605 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
606 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
617 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
618 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
629 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
630 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
641 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
642 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
643 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
650 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
651 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
652 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
659 /* LNK_LED_REG 8 bit Link LED Register */
671 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
672 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
673 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
674 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
675 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
676 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
677 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
678 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
679 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
683 /* TXA_TEST 8 bit Tx Arbiter Test Register */
693 /* TXA_STAT 8 bit Tx Arbiter Status Register */
699 /* Q_BC 32 bit Current Byte Counter */
702 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
703 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
704 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
705 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
706 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
707 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
708 /* Q_CSR 32 bit BMU Control/Status Register */
744 /* Q_F 32 bit Flag Register */
748 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
756 /* RB_START 32 bit RAM Buffer Start Address */
757 /* RB_END 32 bit RAM Buffer End Address */
758 /* RB_WP 32 bit RAM Buffer Write Pointer */
759 /* RB_RP 32 bit RAM Buffer Read Pointer */
760 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
761 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
762 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
763 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
764 /* RB_PC 32 bit RAM Buffer Packet Counter */
765 /* RB_LEV 32 bit RAM Buffer Level Register */
768 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
769 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
771 /* RB_CTRL 8 bit RAM Buffer Control Register */
783 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
784 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
785 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
786 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
787 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
788 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
789 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
790 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
792 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
793 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
794 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
796 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
797 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
798 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
799 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
818 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
819 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
820 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
822 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
823 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
824 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
826 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
827 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
828 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
831 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
832 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
833 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
835 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
838 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
839 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
840 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
855 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
856 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
857 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
858 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
859 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
865 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
866 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
867 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
868 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
869 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
873 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
874 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
878 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
879 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
926 * XMR_FS_ERR unless the corresponding bit in the Receive Command
935 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
936 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
937 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
938 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
939 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
940 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
941 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
942 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
943 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
945 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
946 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
952 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
953 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
954 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
955 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
956 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
957 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
958 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
959 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
960 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
962 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
963 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
964 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
965 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
966 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
967 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
968 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
969 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
971 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
972 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
973 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
974 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
981 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
982 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
983 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
984 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
985 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
986 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
987 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
988 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
989 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
991 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
992 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
993 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
994 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
995 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
996 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
997 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
998 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
999 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1000 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1001 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1002 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1003 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1004 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1005 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1006 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1007 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1008 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1011 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1012 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1013 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1014 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1015 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1021 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1028 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1112 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1118 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1136 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1146 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1147 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1159 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1167 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1187 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1205 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1206 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1215 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1219 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1223 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1228 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1237 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1256 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1257 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1326 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1336 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1378 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1430 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1463 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1507 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1524 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1533 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1544 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1549 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1569 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1600 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1608 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1624 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1625 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1626 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1627 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1628 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1629 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1630 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1632 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1633 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1634 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1635 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1636 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1637 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1640 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1641 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1642 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1643 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1646 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1647 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1648 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1651 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1652 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1653 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1656 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1657 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1658 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1667 * use offset 4 for access to high word (32 bit r/o)
1717 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1735 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1757 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1768 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1776 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1792 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1807 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1819 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1855 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1877 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1888 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1895 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1907 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1958 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1959 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1970 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1976 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2003 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2009 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2010 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2011 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2012 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2013 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2014 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2015 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2016 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2017 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2018 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2019 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2020 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2021 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2022 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2023 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2024 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2025 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2026 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2027 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2028 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2030 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2031 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2032 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2033 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2042 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2043 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2044 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2045 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2046 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2047 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2049 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2050 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2051 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2052 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2053 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2054 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2055 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2056 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2057 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2058 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2059 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2060 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2061 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2062 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2063 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2064 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2065 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2066 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2067 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2068 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2069 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2070 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2071 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2072 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2073 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2074 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2075 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2076 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2077 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2078 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2079 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2080 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2081 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2082 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2083 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2084 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2085 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2086 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2087 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2088 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2089 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2090 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2091 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2092 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2093 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2094 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2095 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2096 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2097 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2098 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2099 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2100 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2101 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2102 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2103 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2104 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2105 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2106 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2107 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2108 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2109 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2110 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2113 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2130 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2141 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2145 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2149 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2153 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2155 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2157 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2169 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2179 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2180 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2184 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2185 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2201 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2209 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2210 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2213 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2214 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2215 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2219 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2238 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2239 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2243 /* XM_DEV_ID 32 bit r/o Device ID Register */
2248 /* XM_MODE 32 bit r/w Mode Register */
2287 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2298 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2299 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2335 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2336 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
H A Dsky2.h59 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
90 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
113 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
156 /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
371 /* B0_CTST 24 bit Control/Status register */
406 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
408 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
409 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
410 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
411 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
448 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
500 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
506 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
532 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
540 /* B2_CHIP_ID 8 bit Chip Identification Number */
595 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
607 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
617 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
629 /* B2_TI_CTRL 8 bit Timer control */
630 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
638 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
639 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
652 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
657 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
673 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
674 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
675 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
676 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
680 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
697 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
698 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
699 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
700 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
701 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
702 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
703 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
735 Q_D = 0x00, /* 8*32 bit Current Descriptor */
736 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
737 Q_DONE = 0x24, /* 16 bit Done Index */
738 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
739 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
740 Q_BC = 0x30, /* 32 bit Current Byte Counter */
741 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
742 Q_TEST = 0x38, /* 32 bit Test/Control Register */
745 Q_WM = 0x40, /* 16 bit FIFO Watermark */
746 Q_AL = 0x42, /* 8 bit FIFO Alignment */
747 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
748 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
749 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
750 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
751 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
752 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
753 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
754 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
758 /* Q_TEST 32 bit Test Register */
774 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
775 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
776 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
777 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
778 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
779 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
780 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
781 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
782 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
783 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
792 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
793 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
794 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
795 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
796 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
797 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
798 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
799 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
801 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
802 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
803 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
804 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
805 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
827 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
828 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
829 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
830 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
832 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
836 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
837 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
838 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
839 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
840 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
841 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
842 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
843 RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
844 RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
845 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
846 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
848 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
850 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
852 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
856 /* Q_BC 32 bit Current Byte Counter */
859 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
860 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
861 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
862 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
863 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
864 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
865 /* Q_CSR 32 bit BMU Control/Status Register */
944 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
953 /* RB_START 32 bit RAM Buffer Start Address */
954 /* RB_END 32 bit RAM Buffer End Address */
955 /* RB_WP 32 bit RAM Buffer Write Pointer */
956 /* RB_RP 32 bit RAM Buffer Read Pointer */
957 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
958 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
959 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
960 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
961 /* RB_PC 32 bit RAM Buffer Packet Counter */
962 /* RB_LEV 32 bit RAM Buffer Level Register */
965 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
966 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
968 /* RB_CTRL 8 bit RAM Buffer Control Register */
981 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
982 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
983 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
985 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
986 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
987 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
989 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
990 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
991 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
1001 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
1002 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
1003 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
1005 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
1010 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
1011 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
1012 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
1017 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
1018 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
1020 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
1021 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
1025 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
1026 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
1030 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
1031 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
1032 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
1033 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
1034 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
1035 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
1036 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
1037 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
1038 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
1039 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
1044 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
1045 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
1046 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
1048 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
1049 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
1050 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
1051 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
1052 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
1053 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
1058 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
1059 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
1061 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
1062 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
1063 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
1064 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
1065 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
1066 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
1067 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
1068 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
1071 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
1072 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
1073 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
1074 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
1075 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
1076 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
1077 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
1080 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
1081 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
1082 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
1083 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
1084 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
1085 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
1086 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
1087 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
1088 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
1089 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
1090 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
1091 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
1105 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
1106 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
1107 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
1108 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
1109 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
1112 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
1113 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
1114 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
1115 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
1116 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
1119 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
1120 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
1123 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
1124 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
1143 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1144 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1145 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1146 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1147 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1148 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1149 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1150 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1151 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1153 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1154 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1155 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1156 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1157 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1158 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1159 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1160 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1161 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1162 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1163 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1164 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1165 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1166 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1167 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1168 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1169 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1170 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1173 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1174 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1175 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1176 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1177 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1183 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1190 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1254 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1255 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1299 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1309 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1359 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1411 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1459 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1483 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1521 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1538 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1547 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1558 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1564 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1595 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1603 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1611 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1621 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1637 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1638 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1639 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1640 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1641 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1642 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1643 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1645 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1646 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1647 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1648 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1649 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1650 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1653 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1654 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1655 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1656 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1659 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1660 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1661 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1664 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1665 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1666 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1669 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1670 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1671 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1680 * use offset 4 for access to high word (32 bit r/o)
1729 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1747 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1768 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1779 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1787 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1806 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1825 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1837 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1867 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1912 /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1926 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1931 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1951 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1958 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1970 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
2009 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2018 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2039 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2067 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2068 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2080 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2087 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2376 /* There is no way to atomically read32 bit values from PHY, so retry */ get_stats32()
/linux-4.1.27/fs/ocfs2/
H A Dheartbeat.c44 int bit);
46 int bit);
85 int bit) __ocfs2_node_map_set_bit()
87 set_bit(bit, map->map); __ocfs2_node_map_set_bit()
92 int bit) ocfs2_node_map_set_bit()
94 if (bit==-1) ocfs2_node_map_set_bit()
96 BUG_ON(bit >= map->num_nodes); ocfs2_node_map_set_bit()
98 __ocfs2_node_map_set_bit(map, bit); ocfs2_node_map_set_bit()
103 int bit) __ocfs2_node_map_clear_bit()
105 clear_bit(bit, map->map); __ocfs2_node_map_clear_bit()
110 int bit) ocfs2_node_map_clear_bit()
112 if (bit==-1) ocfs2_node_map_clear_bit()
114 BUG_ON(bit >= map->num_nodes); ocfs2_node_map_clear_bit()
116 __ocfs2_node_map_clear_bit(map, bit); ocfs2_node_map_clear_bit()
122 int bit) ocfs2_node_map_test_bit()
125 if (bit >= map->num_nodes) { ocfs2_node_map_test_bit()
126 mlog(ML_ERROR, "bit=%d map->num_nodes=%d\n", bit, map->num_nodes); ocfs2_node_map_test_bit()
130 ret = test_bit(bit, map->map); ocfs2_node_map_test_bit()
84 __ocfs2_node_map_set_bit(struct ocfs2_node_map *map, int bit) __ocfs2_node_map_set_bit() argument
90 ocfs2_node_map_set_bit(struct ocfs2_super *osb, struct ocfs2_node_map *map, int bit) ocfs2_node_map_set_bit() argument
102 __ocfs2_node_map_clear_bit(struct ocfs2_node_map *map, int bit) __ocfs2_node_map_clear_bit() argument
108 ocfs2_node_map_clear_bit(struct ocfs2_super *osb, struct ocfs2_node_map *map, int bit) ocfs2_node_map_clear_bit() argument
120 ocfs2_node_map_test_bit(struct ocfs2_super *osb, struct ocfs2_node_map *map, int bit) ocfs2_node_map_test_bit() argument
/linux-4.1.27/arch/xtensa/include/asm/
H A Dbitops.h39 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
48 * __ffs: Find first bit set in word. Return 0 for bit 0
57 * ffs: Find first bit set in word. This is defined the same way as
68 * fls: Find last (most-significant) bit set in word.
78 * __fls - find last (most-significant) set bit in a long word
81 * Undefined if no set bit exists, so code should check against 0 first.
103 static inline void set_bit(unsigned int bit, volatile unsigned long *p) set_bit() argument
106 unsigned long mask = 1UL << (bit & 31); set_bit()
108 p += bit >> 5; set_bit()
121 static inline void clear_bit(unsigned int bit, volatile unsigned long *p) clear_bit() argument
124 unsigned long mask = 1UL << (bit & 31); clear_bit()
126 p += bit >> 5; clear_bit()
139 static inline void change_bit(unsigned int bit, volatile unsigned long *p) change_bit() argument
142 unsigned long mask = 1UL << (bit & 31); change_bit()
144 p += bit >> 5; change_bit()
158 test_and_set_bit(unsigned int bit, volatile unsigned long *p) test_and_set_bit() argument
161 unsigned long mask = 1UL << (bit & 31); test_and_set_bit()
163 p += bit >> 5; test_and_set_bit()
179 test_and_clear_bit(unsigned int bit, volatile unsigned long *p) test_and_clear_bit() argument
182 unsigned long mask = 1UL << (bit & 31); test_and_clear_bit()
184 p += bit >> 5; test_and_clear_bit()
200 test_and_change_bit(unsigned int bit, volatile unsigned long *p) test_and_change_bit() argument
203 unsigned long mask = 1UL << (bit & 31); test_and_change_bit()
205 p += bit >> 5; test_and_change_bit()
H A Dmxregs.h24 * 0190 0...0x..x 8-bit IPI partition register
26 * V (10-bit) Release/Version
27 * P ( 4-bit) Number of cores - 1
28 * U (18-bit) ID
29 * 01a0 i.......i 32-bit ConfigID
/linux-4.1.27/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c40 "vphn: 1 x 16-bit value",
55 "vphn: 2 x 16-bit values",
71 "vphn: 3 x 16-bit values",
88 "vphn: 4 x 16-bit values",
106 /* Parsing the next 16-bit value out of the next 64-bit input
109 "vphn: 5 x 16-bit values",
128 /* Parse at most 6 x 64-bit input values */
129 "vphn: 24 x 16-bit values",
167 "vphn: 1 x 32-bit value",
182 "vphn: 2 x 32-bit values",
198 /* Parsing the next 32-bit value out of the next 64-bit input
201 "vphn: 3 x 32-bit values",
218 /* Parse at most 6 x 64-bit input values */
219 "vphn: 12 x 32-bit values",
245 "vphn: 16-bit value followed by 32-bit value",
261 "vphn: 32-bit value followed by 16-bit value",
277 /* Parse a 32-bit value split accross two consecutives 64-bit
280 "vphn: 16-bit value followed by 2 x 32-bit values",
302 "vphn: 32-bit value has all ones in 16 lower bits",
321 "vphn: last 32-bit value is truncated",
H A Dvphn.h4 /* The H_HOME_NODE_ASSOCIATIVITY h_call returns 6 64-bit registers.
9 * 6 64-bit registers unpacked into up to 24 be32 associativity values. To
/linux-4.1.27/drivers/mmc/host/
H A Dpxamci.h19 #define MMC_CLKRT 0x0008 /* 3 bit */
41 #define MMC_RESTO 0x0014 /* 7 bit */
43 #define MMC_RDTO 0x0018 /* 16 bit */
45 #define MMC_BLKLEN 0x001c /* 10 bit */
47 #define MMC_NOB 0x0020 /* 16 bit */
82 #define MMC_ARGH 0x0034 /* 16 bit */
84 #define MMC_ARGL 0x0038 /* 16 bit */
86 #define MMC_RES 0x003c /* 16 bit */
88 #define MMC_RXFIFO 0x0040 /* 8 bit */
90 #define MMC_TXFIFO 0x0044 /* 8 bit */
/linux-4.1.27/arch/x86/lib/
H A Dmsr.c58 static inline int __flip_bit(u32 msr, u8 bit, bool set) __flip_bit() argument
63 if (bit > 63) __flip_bit()
72 m1.q |= BIT_64(bit); __flip_bit()
74 m1.q &= ~BIT_64(bit); __flip_bit()
87 * Set @bit in a MSR @msr.
94 int msr_set_bit(u32 msr, u8 bit) msr_set_bit() argument
96 return __flip_bit(msr, bit, true); msr_set_bit()
100 * Clear @bit in a MSR @msr.
107 int msr_clear_bit(u32 msr, u8 bit) msr_clear_bit() argument
109 return __flip_bit(msr, bit, false); msr_clear_bit()
/linux-4.1.27/drivers/net/fddi/skfp/h/
H A Dskfbi.h34 #define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
35 #define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
36 #define PCI_COMMAND 0x04 /* 16 bit Command */
37 #define PCI_STATUS 0x06 /* 16 bit Status */
38 #define PCI_REV_ID 0x08 /* 8 bit Revision ID */
39 #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
40 #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
41 #define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
42 #define PCI_HEADER_T 0x0e /* 8 bit Header Type */
43 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
44 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
45 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
47 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
48 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
49 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
51 #define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */
53 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
54 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
55 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
56 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
58 #define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */
59 #define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */
60 #define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */
62 #define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */
63 #define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */
64 #define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */
65 #define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */
67 #define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */
69 #define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */
70 #define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */
71 #define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */
72 #define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */
86 /* PCI_VENDOR_ID 16 bit Vendor ID */
87 /* PCI_DEVICE_ID 16 bit Device ID */
89 /* PCI_COMMAND 16 bit Command */
101 /* PCI_STATUS 16 bit Status */
119 /* PCI_REV_ID 8 bit Revision ID */
120 /* PCI_CLASS_CODE 24 bit Class Code */
125 /* PCI_CACHE_LSZ 8 bit Cache Line Size */
128 /* PCI_LAT_TIM 8 bit Latency Timer */
130 /* PCI_HEADER_T 8 bit Header Type */
134 /* PCI_BIST 8 bit Built-in selftest */
139 /* PCI_BASE_1ST 32 bit 1st Base address */
150 /* PCI_SUB_VID 16 bit Subsystem Vendor ID */
151 /* PCI_SUB_ID 16 bit Subsystem ID */
153 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
159 /* PCI_CAP_PTR 8 bit New Capabilities Pointers */
160 /* PCI_IRQ_LINE 8 bit Interrupt Line */
161 /* PCI_IRQ_PIN 8 bit Interrupt Pin */
162 /* PCI_MIN_GNT 8 bit Min_Gnt */
163 /* PCI_MAX_LAT 8 bit Max_Lat */
165 /* PCI_OUR_REG (DV) 32 bit Our Register */
166 /* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */
201 /* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */
222 /* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */
223 /* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */
224 /* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/
234 /* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */
245 /* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */
247 /* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */
248 /* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */
249 /* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */
252 /* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */
258 #define B0_RAP 0x0000 /* 8 bit register address port */
260 #define B0_CTRL 0x0004 /* 8 bit control register */
263 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
264 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
265 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
270 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
271 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
272 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
273 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
277 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
278 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
281 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
282 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
283 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
284 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
299 #define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */
300 #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/
301 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */
302 #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */
313 #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */
314 #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */
315 #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */
316 #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */
317 #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */
318 #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */
319 #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */
320 #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */
322 #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */
323 #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */
326 #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */
327 #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */
328 #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */
329 #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */
330 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
331 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
333 #define B2_LD_CRTL 0x0118 /* 8 bit loader control */
334 #define B2_LD_TEST 0x0119 /* 8 bit loader test */
336 #define B2_TI_INI 0x0120 /* 32 bit Timer init value */
337 #define B2_TI_VAL 0x0124 /* 32 bit Timer value */
338 #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */
341 #define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */
342 #define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */
343 #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */
346 #define B2_RTM_INI 0x0140 /* 32 bit RTM init value */
347 #define B2_RTM_VAL 0x0144 /* 32 bit RTM value */
348 #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
351 #define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */
352 #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */
353 #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
354 #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
356 #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
357 #define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */
358 #define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */
360 #define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */
361 #define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */
362 #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
363 #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
377 #define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */
378 #define B4_R1_DA 0x0210 /* 32 bit current rec desc address */
379 #define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */
380 #define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */
381 #define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */
382 #define B4_R1_F 0x0220 /* 32 bit flag register */
383 #define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */
384 #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */
385 #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
386 #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */
387 #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */
388 #define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */
389 #define B4_R1_T3 0x022c /* 32 bit Test Register 3 */
390 #define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */
391 #define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */
394 #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */
395 #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */
396 #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */
397 #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */
398 #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */
399 #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */
400 #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */
401 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
402 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
403 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
404 #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
405 #define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */
406 #define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */
412 #define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */
413 #define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */
414 #define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */
415 #define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */
416 #define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */
417 #define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */
418 #define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */
419 #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */
420 #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
421 #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */
422 #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */
423 #define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */
424 #define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */
425 #define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */
426 #define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */
428 #define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */
429 #define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */
430 #define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */
431 #define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */
432 #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */
433 #define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */
434 #define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */
435 #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
436 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
437 #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
438 #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
439 #define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */
440 #define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */
441 #define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */
442 #define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */
465 /* B0_RAP 16 bit register address port */
468 /* B0_CTRL 8 bit control register */
480 #define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/
504 /* B0_TST_CTRL 8 bit test control register */
514 /* B0_ISRC 32 bit Interrupt source register */
561 /* B0_IMSK 32 bit Interrupt mask register */
604 /* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */
605 /* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */
606 /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */
607 /* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */
610 /* B2_MAC_0 8 bit MAC address Byte 0 */
611 /* B2_MAC_1 8 bit MAC address Byte 1 */
612 /* B2_MAC_2 8 bit MAC address Byte 2 */
613 /* B2_MAC_3 8 bit MAC address Byte 3 */
614 /* B2_MAC_4 8 bit MAC address Byte 4 */
615 /* B2_MAC_5 8 bit MAC address Byte 5 */
616 /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */
617 /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */
619 /* B2_CONN_TYP 8 bit Connector type */
620 /* B2_PMD_TYP 8 bit PMD type */
624 /* B2_E_0 8 bit EPROM Byte 0 */
625 /* B2_E_1 8 bit EPROM Byte 1 */
626 /* B2_E_2 8 bit EPROM Byte 2 */
627 /* B2_E_3 8 bit EPROM Byte 3 */
629 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
632 /* B2_FDP 8 bit Flash-Prom Data Port */
634 /* B2_LD_CRTL 8 bit loader control */
637 /* B2_LD_TEST 8 bit loader test */
643 /* B2_TI_INI 32 bit Timer init value */
644 /* B2_TI_VAL 32 bit Timer value */
645 /* B2_TI_CRTL 8 bit Timer control */
647 /* B2_WDOG_INI 32 bit Watchdog init value */
648 /* B2_WDOG_VAL 32 bit Watchdog value */
649 /* B2_WDOG_CRTL 8 bit Watchdog control */
651 /* B2_RTM_INI 32 bit RTM init value */
652 /* B2_RTM_VAL 32 bit RTM value */
653 /* B2_RTM_CRTL 8 bit RTM control */
655 /* B2_<TIM>_CRTL 8 bit <TIM> control */
656 /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */
657 /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */
658 /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */
659 /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */
671 /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */
672 /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */
673 /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
681 /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
688 /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
697 /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */
723 /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */
725 /* B4_R1_D 4*32 bit current receive Descriptor (q1) */
726 /* B4_R1_DA 32 bit current rec desc address (q1) */
727 /* B4_R1_AC 32 bit current receive Address Count (q1) */
728 /* B4_R1_BC 32 bit current receive Byte Counter (q1) */
729 /* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */
730 /* B4_R1_F 32 bit flag register (q1) */
731 /* B4_R1_T1 32 bit Test Register 1 (q1) */
732 /* B4_R1_T2 32 bit Test Register 2 (q1) */
733 /* B4_R1_T3 32 bit Test Register 3 (q1) */
734 /* B4_R2_D 4*32 bit current receive Descriptor (q2) */
735 /* B4_R2_DA 32 bit current rec desc address (q2) */
736 /* B4_R2_AC 32 bit current receive Address Count (q2) */
737 /* B4_R2_BC 32 bit current receive Byte Counter (q2) */
738 /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */
739 /* B4_R2_F 32 bit flag register (q2) */
740 /* B4_R2_T1 32 bit Test Register 1 (q2) */
741 /* B4_R2_T2 32 bit Test Register 2 (q2) */
742 /* B4_R2_T3 32 bit Test Register 3 (q2) */
743 /* B5_XA_D 4*32 bit current receive Descriptor (xa) */
744 /* B5_XA_DA 32 bit current rec desc address (xa) */
745 /* B5_XA_AC 32 bit current receive Address Count (xa) */
746 /* B5_XA_BC 32 bit current receive Byte Counter (xa) */
747 /* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */
748 /* B5_XA_F 32 bit flag register (xa) */
749 /* B5_XA_T1 32 bit Test Register 1 (xa) */
750 /* B5_XA_T2 32 bit Test Register 2 (xa) */
751 /* B5_XA_T3 32 bit Test Register 3 (xa) */
752 /* B5_XS_D 4*32 bit current receive Descriptor (xs) */
753 /* B5_XS_DA 32 bit current rec desc address (xs) */
754 /* B5_XS_AC 32 bit current receive Address Count (xs) */
755 /* B5_XS_BC 32 bit current receive Byte Counter (xs) */
756 /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */
757 /* B5_XS_F 32 bit flag register (xs) */
758 /* B5_XS_T1 32 bit Test Register 1 (xs) */
759 /* B5_XS_T2 32 bit Test Register 2 (xs) */
760 /* B5_XS_T3 32 bit Test Register 3 (xs) */
761 /* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */
789 /* B5_<xx>_F 32 bit flag register (xx) */
792 #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */
801 /* B5_<xx>_T1 32 bit Test Register 1 (xx) */
808 /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */
809 /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */
810 /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */
811 /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */
858 /* B5_<xx>_T2 32 bit Test Register 2 (xx) */
870 /* B5_<xx>_T3 32 bit Test Register 3 (xx) */
912 #define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */
1003 * 12 bit transfer (dword) counter:
1064 /* read FORMAC+ 32-bit status register */
1074 /* read FORMAC+ 32-bit status register */
1083 /* timer access over data bus bit 8..15 */
/linux-4.1.27/include/uapi/linux/
H A Dswab.h102 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
120 * __swab64 - return a byteswapped 64-bit value
129 * __swahw32 - return a word-swapped 32-bit value
140 * __swahb32 - return a high and low byte-swapped 32-bit value
151 * __swab16p - return a byteswapped 16-bit value from a pointer
152 * @p: pointer to a naturally-aligned 16-bit value
164 * __swab32p - return a byteswapped 32-bit value from a pointer
165 * @p: pointer to a naturally-aligned 32-bit value
177 * __swab64p - return a byteswapped 64-bit value from a pointer
178 * @p: pointer to a naturally-aligned 64-bit value
190 * __swahw32p - return a wordswapped 32-bit value from a pointer
191 * @p: pointer to a naturally-aligned 32-bit value
205 * __swahb32p - return a high and low byteswapped 32-bit value from a pointer
206 * @p: pointer to a naturally-aligned 32-bit value
220 * __swab16s - byteswap a 16-bit value in-place
221 * @p: pointer to a naturally-aligned 16-bit value
232 * __swab32s - byteswap a 32-bit value in-place
233 * @p: pointer to a naturally-aligned 32-bit value
245 * __swab64s - byteswap a 64-bit value in-place
246 * @p: pointer to a naturally-aligned 64-bit value
258 * __swahw32s - wordswap a 32-bit value in-place
259 * @p: pointer to a naturally-aligned 32-bit value
273 * __swahb32s - high and low byteswap a 32-bit value in-place
274 * @p: pointer to a naturally-aligned 32-bit value
H A Dsecurebits.h4 /* Each securesetting is implemented using two bits. One bit specifies
5 whether the setting is on or off. The other bit specify whether the
16 0. If the real uid is 0, we raise the effective (legacy) bit of the
19 #define SECURE_NOROOT_LOCKED 1 /* make bit-0 immutable */
29 #define SECURE_NO_SETUID_FIXUP_LOCKED 3 /* make bit-2 immutable */
37 bit 2). Bit-4 is cleared when a process calls exec(); setting both
38 bit 4 and 5 will create a barrier through exec that no exec()'d
41 #define SECURE_KEEP_CAPS_LOCKED 5 /* make bit-4 immutable */
H A Dtypes.h44 * common 32/64-bit compat problems.
45 * 64-bit values align to 4-byte boundaries on x86_32 (and possibly other
46 * architectures) and to 8-byte boundaries on 64-bit architectures. The new
48 * aligned_64 values have the same alignment on 32-bit and 64-bit architectures.
49 * No conversions are necessary between 32-bit user-space and a 64-bit kernel.
H A Dcm4000_cs.h25 * member sizes. This leads to CONFIG_COMPAT breakage, since 32bit userspace
26 * will lay out the structure members differently than the 64bit kernel.
29 * On 32bit this will make no difference. With 64bit kernels, it will make
30 * 32bit apps work, too.
/linux-4.1.27/drivers/acpi/pmic/
H A Dintel_pmic_xpower.c30 .bit = 0x05,
35 .bit = 0x06,
40 .bit = 0x07,
45 .bit = 0x03,
50 .bit = 0x04,
55 .bit = 0x05,
60 .bit = 0x06,
65 .bit = 0x00,
70 .bit = 0x01,
75 .bit = 0x02,
80 .bit = 0x02,
85 .bit = 0x03,
90 .bit = 0x04,
95 .bit = 0x03,
100 .bit = 0x06,
105 .bit = 0x05,
110 .bit = 0x04,
115 .bit = 0x01,
120 .bit = 0x00
153 int bit, u64 *value) intel_xpower_pmic_get_power()
160 *value = (data & BIT(bit)) ? 1 : 0; intel_xpower_pmic_get_power()
165 int bit, bool on) intel_xpower_pmic_update_power()
173 data |= BIT(bit); intel_xpower_pmic_update_power()
175 data &= ~BIT(bit); intel_xpower_pmic_update_power()
152 intel_xpower_pmic_get_power(struct regmap *regmap, int reg, int bit, u64 *value) intel_xpower_pmic_get_power() argument
164 intel_xpower_pmic_update_power(struct regmap *regmap, int reg, int bit, bool on) intel_xpower_pmic_update_power() argument
H A Dintel_pmic.h7 int bit; /* control bit for power */ member in struct:pmic_table
11 int (*get_power)(struct regmap *r, int reg, int bit, u64 *value);
12 int (*update_power)(struct regmap *r, int reg, int bit, bool on);
/linux-4.1.27/arch/sh/include/mach-se/mach/
H A Dmrshpc.h24 /* common mode & bus width 16bit SWAP = 1*/ mrshpc_setup_windows()
27 /* common mode & bus width 16bit SWAP = 0*/ mrshpc_setup_windows()
33 /* attribute mode & bus width 16bit SWAP = 1*/ mrshpc_setup_windows()
36 /* attribute mode & bus width 16bit SWAP = 0*/ mrshpc_setup_windows()
43 __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ mrshpc_setup_windows()
45 __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ mrshpc_setup_windows()
/linux-4.1.27/arch/powerpc/include/asm/
H A Dpte-fsl-booke.h5 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
26 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
27 #define _PAGE_GUARDED 0x00080 /* H: G bit */
28 #define _PAGE_COHERENT 0x00100 /* H: M bit */
29 #define _PAGE_NO_CACHE 0x00200 /* H: I bit */
30 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
H A Dbitops.h2 * PowerPC atomic bit operations.
13 * bit depends on the word size.
22 * bitmaps, these work on similar bit arrays layouts, but
26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
27 * number field needs to be reversed compared to the big-endian bit
49 /* PPC bit number conversion */
51 #define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
166 * Return the zero-based bit position (LE, not IBM bit numbering) of
167 * the most significant 1-bit in a double word.
181 int bit; __ilog2_u32() local
182 asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n)); __ilog2_u32()
183 return 31 - bit; __ilog2_u32()
190 int bit; __ilog2_u64() local
191 asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n)); __ilog2_u64()
192 return 63 - bit; __ilog2_u64()
197 * Determines the bit position of the least significant 0 bit in the
198 * specified double word. The returned bit position will be
208 * Calculate the bit position of the least significant '1' bit in x ffz()
210 * '0' bit in * the original x). Note: (x & -x) gives us a mask that ffz()
211 * is the least significant * (RIGHT-most) 1-bit of the value in x. ffz()
222 * ffs: find first bit set. This is defined the same way as
233 * fls: find last (most-significant) bit set.
250 * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
251 * instruction; for 32-bit we use the generic version, which does two
252 * 32-bit fls calls.
H A Ddbdma.h19 unsigned int intr_sel; /* select interrupt condition bit */
20 unsigned int br_sel; /* select branch condition bit */
21 unsigned int wait_sel; /* select wait condition bit */
46 __le16 command; /* command word (has bit-fields) */
74 #define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75 #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
80 #define BR_IFSET 0x4 /* branch if condition bit is 1 */
81 #define BR_IFCLR 0x8 /* branch if condition bit is 0 */
86 #define WAIT_IFSET 1 /* wait if condition bit is 1 */
87 #define WAIT_IFCLR 2 /* wait if condition bit is 0 */
/linux-4.1.27/tools/include/asm-generic/bitops/
H A Dfind.h6 * find_next_bit - find the next set bit in a memory region
11 * Returns the bit number for the next set bit
21 * find_first_bit - find the first set bit in a memory region
25 * Returns the bit number of the first set bit.
H A D__ffs.h7 * __ffs - find first bit in word.
10 * Undefined if no bit exists, so code should check against 0 first.
/linux-4.1.27/arch/arm/include/asm/
H A Dbitops.h8 * bit 0 is the LSB of an "unsigned long" quantity.
31 * These functions are the basis of our bit ops.
35 static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p) ____atomic_set_bit() argument
38 unsigned long mask = 1UL << (bit & 31); ____atomic_set_bit()
40 p += bit >> 5; ____atomic_set_bit()
47 static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) ____atomic_clear_bit() argument
50 unsigned long mask = 1UL << (bit & 31); ____atomic_clear_bit()
52 p += bit >> 5; ____atomic_clear_bit()
59 static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) ____atomic_change_bit() argument
62 unsigned long mask = 1UL << (bit & 31); ____atomic_change_bit()
64 p += bit >> 5; ____atomic_change_bit()
72 ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) ____atomic_test_and_set_bit() argument
76 unsigned long mask = 1UL << (bit & 31); ____atomic_test_and_set_bit()
78 p += bit >> 5; ____atomic_test_and_set_bit()
89 ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) ____atomic_test_and_clear_bit() argument
93 unsigned long mask = 1UL << (bit & 31); ____atomic_test_and_clear_bit()
95 p += bit >> 5; ____atomic_test_and_clear_bit()
106 ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) ____atomic_test_and_change_bit() argument
110 unsigned long mask = 1UL << (bit & 31); ____atomic_test_and_change_bit()
112 p += bit >> 5; ____atomic_test_and_change_bit()
136 * This means that reading a 32-bit word at address 0 returns the same
137 * value irrespective of the endian mode bit.
146 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
150 * Native endian assembly bitops. nr = 0 -> word 0 bit 0.
160 * Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
168 * Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
270 * fls() returns zero if the input is zero, otherwise returns the bit
271 * position of the last set bit, where the LSB is 1 and MSB is 32.
282 * __fls() returns the bit position of the last bit set, where the
291 * ffs() returns zero if the input was zero, otherwise returns the bit
292 * position of the first set bit, where the LSB is 1 and MSB is 32.
300 * __ffs() returns the bit position of the first bit set, where the
/linux-4.1.27/include/media/
H A Dsh_mobile_ceu.h4 #define SH_CEU_FLAG_USE_8BIT_BUS (1 << 0) /* use 8bit bus width */
5 #define SH_CEU_FLAG_USE_16BIT_BUS (1 << 1) /* use 16bit bus width */
8 #define SH_CEU_FLAG_LOWER_8BIT (1 << 4) /* default upper 8bit */
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A Dreg_wow.h31 * bit 31:24 pattern 0 length
32 * bit 23:16 pattern 1 length
33 * bit 15:8 pattern 2 length
34 * bit 7:0 pattern 3 length
37 * bit 31:24 pattern 4 length
38 * bit 23:16 pattern 5 length
39 * bit 15:8 pattern 6 length
40 * bit 7:0 pattern 7 length
43 * bit 31:24 pattern 8 length
44 * bit 23:16 pattern 9 length
45 * bit 15:8 pattern 10 length
46 * bit 7:0 pattern 11 length
49 * bit 31:24 pattern 12 length
50 * bit 23:16 pattern 13 length
51 * bit 15:8 pattern 14 length
52 * bit 7:0 pattern 15 length
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Dmman.h4 #define MAP_32BIT 0x40 /* only give out 32bit addresses */
H A Dldt.h16 * Note on 64bit base and limit is ignored and you cannot set DS/ES/CS
18 * call is more for 32bit mode therefore.
32 * Because this bit is not present in 32-bit user code, user
34 * any context in which a user_desc comes from a 32-bit program,
H A Dunistd.h4 /* x32 syscall flag bit */
H A Dsembuf.h10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
/linux-4.1.27/include/uapi/asm-generic/
H A Dipcbuf.h14 * - 32-bit mode_t on architectures that only had 16 bit
15 * - 32-bit seq
16 * - 2 miscellaneous 32-bit values
H A Dbitsperlong.h6 * space, so 64 bit architectures should override this in their
8 * both 32 and 64 bit user space must not rely on CONFIG_64BIT
H A Dswab.h7 * 32 bit architectures typically (but not always) want to
9 * valid if the compiler supports 64 bit data types.
H A Dsembuf.h15 * 64 bit architectures typically define a 64 bit __kernel_time_t,
20 * - 64-bit time_t to solve y2038 problem
21 * - 2 miscellaneous 32-bit values
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
H A Dserial-sh7720.c14 /* Clear PTCR bit 9-2; enable all scif pins but sck */ sh7720_sci_init_pins()
18 /* Clear PVCR bit 9-2 */ sh7720_sci_init_pins()
24 /* Clear PTCR bit 5-2; enable only tx and rx */ sh7720_sci_init_pins()
28 /* Clear PVCR bit 5-2 */ sh7720_sci_init_pins()
/linux-4.1.27/arch/parisc/kernel/
H A Dsys_parisc32.c2 * sys_parisc32.c: Conversion between 32bit and 64bit native syscalls.
9 * These routines maintain argument size conversion between 32bit and 64bit
/linux-4.1.27/tools/testing/selftests/powerpc/stringloops/
H A DMakefile1 # The loops are all 64-bit code
/linux-4.1.27/tools/testing/selftests/x86/
H A Dtrivial_32bit_program.c2 * Trivial program to check that we have a valid 32-bit build environment.
H A Dtrivial_64bit_program.c2 * Trivial program to check that we have a valid 32-bit build environment.
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dplatsmp-apmu.c30 int bit; member in struct:__anon270
37 static int __maybe_unused apmu_power_on(void __iomem *p, int bit) apmu_power_on() argument
40 writel_relaxed(BIT(bit), p + WUPCR_OFFS); apmu_power_on()
49 static int apmu_power_off(void __iomem *p, int bit) apmu_power_off() argument
52 writel_relaxed(3, p + CPUNCR_OFFS(bit)); apmu_power_off()
56 static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) apmu_power_off_poll() argument
61 if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) apmu_power_off_poll()
74 return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL; apmu_wrap()
77 static void apmu_init_cpu(struct resource *res, int cpu, int bit) apmu_init_cpu() argument
83 apmu_cpus[cpu].bit = bit; apmu_init_cpu()
85 pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); apmu_init_cpu()
88 static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), apmu_parse_cfg() argument
93 int bit, index; apmu_parse_cfg() local
99 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { apmu_parse_cfg()
100 id = apmu_config[k].cpus[bit]; apmu_parse_cfg()
109 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { apmu_parse_cfg()
110 id = apmu_config[k].cpus[bit]; apmu_parse_cfg()
114 fn(&apmu_config[k].iomem, index, bit); apmu_parse_cfg()
/linux-4.1.27/arch/mips/lib/
H A Dbitops.c15 * __mips_set_bit - Atomically set a bit in memory. This is called by
17 * @nr: the bit to set
23 unsigned bit = nr & SZLONG_MASK; __mips_set_bit() local
28 mask = 1UL << bit; __mips_set_bit()
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
45 unsigned bit = nr & SZLONG_MASK; __mips_clear_bit() local
50 mask = 1UL << bit; __mips_clear_bit()
59 * __mips_change_bit - Toggle a bit in memory. This is called by change_bit()
67 unsigned bit = nr & SZLONG_MASK; __mips_change_bit() local
72 mask = 1UL << bit; __mips_change_bit()
81 * __mips_test_and_set_bit - Set a bit and return its old value. This is
90 unsigned bit = nr & SZLONG_MASK; __mips_test_and_set_bit() local
96 mask = 1UL << bit; __mips_test_and_set_bit()
107 * __mips_test_and_set_bit_lock - Set a bit and return its old value. This is
116 unsigned bit = nr & SZLONG_MASK; __mips_test_and_set_bit_lock() local
122 mask = 1UL << bit; __mips_test_and_set_bit_lock()
133 * __mips_test_and_clear_bit - Clear a bit and return its old value. This is
141 unsigned bit = nr & SZLONG_MASK; __mips_test_and_clear_bit() local
147 mask = 1UL << bit; __mips_test_and_clear_bit()
158 * __mips_test_and_change_bit - Change a bit and return its old value. This is
166 unsigned bit = nr & SZLONG_MASK; __mips_test_and_change_bit() local
172 mask = 1UL << bit; __mips_test_and_change_bit()
/linux-4.1.27/drivers/net/wireless/libertas/
H A Dif_spi.h89 /* Host Interrupt Control bit : Wake up */
91 /* Host Interrupt Control bit : WLAN ready */
96 /* Host Interrupt Control bit : Tx auto download */
98 /* Host Interrupt Control bit : Rx auto upload */
100 /* Host Interrupt Control bit : Command auto download */
102 /* Host Interrupt Control bit : Command auto upload */
106 /* Card Interrupt Case bit : Tx download over */
108 /* Card Interrupt Case bit : Rx upload over */
110 /* Card Interrupt Case bit : Command download over */
112 /* Card Interrupt Case bit : Host event */
114 /* Card Interrupt Case bit : Command upload over */
116 /* Card Interrupt Case bit : Power down */
141 /* Host Interrupt Status bit : Tx download ready */
143 /* Host Interrupt Status bit : Rx upload ready */
145 /* Host Interrupt Status bit : Command download ready */
147 /* Host Interrupt Status bit : Card event */
149 /* Host Interrupt Status bit : Command upload ready */
151 /* Host Interrupt Status bit : I/O write FIFO overflow */
153 /* Host Interrupt Status bit : I/O read FIFO underflow */
155 /* Host Interrupt Status bit : Data write FIFO overflow */
157 /* Host Interrupt Status bit : Data read FIFO underflow */
159 /* Host Interrupt Status bit : Command write FIFO overflow */
161 /* Host Interrupt Status bit : Command read FIFO underflow */
165 /* Host Interrupt Status Mask bit : Tx download ready */
167 /* Host Interrupt Status Mask bit : Rx upload ready */
169 /* Host Interrupt Status Mask bit : Command download ready */
171 /* Host Interrupt Status Mask bit : Card event */
173 /* Host Interrupt Status Mask bit : Command upload ready */
175 /* Host Interrupt Status Mask bit : I/O write FIFO overflow */
177 /* Host Interrupt Status Mask bit : I/O read FIFO underflow */
179 /* Host Interrupt Status Mask bit : Data write FIFO overflow */
181 /* Host Interrupt Status Mask bit : Data write FIFO underflow */
183 /* Host Interrupt Status Mask bit : Command write FIFO overflow */
185 /* Host Interrupt Status Mask bit : Command write FIFO underflow */
/linux-4.1.27/drivers/net/ppp/
H A Dppp_mppe.h2 #define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
5 #define MPPE_OPT_40 0x01 /* 40 bit */
6 #define MPPE_OPT_128 0x02 /* 128 bit */
9 #define MPPE_OPT_56 0x08 /* 56 bit */
18 * names above since C and H are the same bit. We could do a u_int32
24 #define MPPE_L_BIT 0x20 /* 40-bit */
25 #define MPPE_S_BIT 0x40 /* 128-bit */
26 #define MPPE_M_BIT 0x80 /* 56-bit, not supported */
29 /* Does not include H bit; used for least significant octet only. */
37 /* H bit */ \
61 /* H bit */ \
/linux-4.1.27/arch/x86/kvm/
H A Dcpuid.h38 return best && (best->ecx & bit(X86_FEATURE_XSAVE)); guest_cpuid_has_xsave()
46 return best && (best->ebx & bit(X86_FEATURE_TSC_ADJUST)); guest_cpuid_has_tsc_adjust()
54 return best && (best->ebx & bit(X86_FEATURE_SMEP)); guest_cpuid_has_smep()
62 return best && (best->ebx & bit(X86_FEATURE_SMAP)); guest_cpuid_has_smap()
70 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE)); guest_cpuid_has_fsgsbase()
78 return best && (best->ecx & bit(X86_FEATURE_OSVW)); guest_cpuid_has_osvw()
86 return best && (best->ecx & bit(X86_FEATURE_PCID)); guest_cpuid_has_pcid()
94 return best && (best->ecx & bit(X86_FEATURE_X2APIC)); guest_cpuid_has_x2apic()
110 return best && (best->edx & bit(X86_FEATURE_GBPAGES)); guest_cpuid_has_gbpages()
118 return best && (best->ebx & bit(X86_FEATURE_RTM)); guest_cpuid_has_rtm()
126 return best && (best->ebx & bit(X86_FEATURE_MPX)); guest_cpuid_has_mpx()
/linux-4.1.27/fs/xfs/libxfs/
H A Dxfs_bit.h22 * XFS bit manipulation routines.
26 * masks with n high/low bits set, 64-bit values
41 /* Get high bit set out of 32-bit argument, -1 if none set */ xfs_highbit32()
47 /* Get high bit set out of 64-bit argument, -1 if none set */ xfs_highbit64()
53 /* Get low bit set out of 32-bit argument, -1 if none set */ xfs_lowbit32()
59 /* Get low bit set out of 64-bit argument, -1 if none set */ xfs_lowbit64()
84 /* Find next set bit in map */
/linux-4.1.27/drivers/s390/cio/
H A Dairq.c193 * Returns the bit number of the first irq in the allocated block of irqs,
194 * or -1UL if no bit is available or the AIRQ_IV_ALLOC flag has not been
199 unsigned long bit, i, flags; airq_iv_alloc() local
204 bit = find_first_bit_inv(iv->avail, iv->bits); airq_iv_alloc()
205 while (bit + num <= iv->bits) { airq_iv_alloc()
207 if (!test_bit_inv(bit + i, iv->avail)) airq_iv_alloc()
212 clear_bit_inv(bit + i, iv->avail); airq_iv_alloc()
213 if (bit + num >= iv->end) airq_iv_alloc()
214 iv->end = bit + num + 1; airq_iv_alloc()
217 bit = find_next_bit_inv(iv->avail, iv->bits, bit + i + 1); airq_iv_alloc()
219 if (bit + num > iv->bits) airq_iv_alloc()
220 bit = -1UL; airq_iv_alloc()
222 return bit; airq_iv_alloc()
229 * @bit: number of the first irq bit to free
232 void airq_iv_free(struct airq_iv *iv, unsigned long bit, unsigned long num) airq_iv_free() argument
240 /* Clear (possibly left over) interrupt bit */ airq_iv_free()
241 clear_bit_inv(bit + i, iv->vector); airq_iv_free()
242 /* Make the bit positions available again */ airq_iv_free()
243 set_bit_inv(bit + i, iv->avail); airq_iv_free()
245 if (bit + num >= iv->end) { airq_iv_free()
246 /* Find new end of bit-field */ airq_iv_free()
257 * @start: bit number to start the search
258 * @end: bit number to end the search
260 * Returns the bit number of the next non-zero interrupt bit, or
266 unsigned long bit; airq_iv_scan() local
268 /* Find non-zero bit starting from 'ivs->next'. */ airq_iv_scan()
269 bit = find_next_bit_inv(iv->vector, end, start); airq_iv_scan()
270 if (bit >= end) airq_iv_scan()
272 clear_bit_inv(bit, iv->vector); airq_iv_scan()
273 return bit; airq_iv_scan()
/linux-4.1.27/arch/sh/boards/mach-x3proto/
H A Dilsel.c40 * 1:1 mapping between the bit position and the IRQ number.
49 static inline unsigned int ilsel_offset(unsigned int bit) ilsel_offset() argument
51 return ILSEL_LEVELS - bit - 1; ilsel_offset()
54 static inline unsigned long mk_ilsel_addr(unsigned int bit) mk_ilsel_addr() argument
56 return ILSEL_BASE + ((ilsel_offset(bit) >> 1) & ~0x1); mk_ilsel_addr()
59 static inline unsigned int mk_ilsel_shift(unsigned int bit) mk_ilsel_shift() argument
61 return (ilsel_offset(bit) & 0x3) << 2; mk_ilsel_shift()
64 static void __ilsel_enable(ilsel_source_t set, unsigned int bit) __ilsel_enable() argument
71 addr = mk_ilsel_addr(bit); __ilsel_enable()
72 shift = mk_ilsel_shift(bit); __ilsel_enable()
74 pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n", __ilsel_enable()
75 __func__, bit, addr, shift, set); __ilsel_enable()
97 unsigned int bit; ilsel_enable() local
105 bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS); ilsel_enable()
106 } while (test_and_set_bit(bit, &ilsel_level_map)); ilsel_enable()
108 __ilsel_enable(set, bit); ilsel_enable()
110 return bit; ilsel_enable()
127 unsigned int bit = ilsel_offset(level - 1); ilsel_enable_fixed() local
129 if (test_and_set_bit(bit, &ilsel_level_map)) ilsel_enable_fixed()
132 __ilsel_enable(set, bit); ilsel_enable_fixed()
134 return bit; ilsel_enable_fixed()
/linux-4.1.27/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8505.c242 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
256 * selected by writing 1 in GPIOSEL bit :
258 * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
267 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
269 * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1=
277 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
278 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
279 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
280 ALTERNATE_FUNCTIONS(4, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO4, bit 3 reserved */
281 ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5, bit 4 reserved */
282 ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6, bit 5 reserved */
283 ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7, bit 6 reserved */
284 ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8, bit 7 reserved */
286 ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */
287 ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
288 ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */
290 ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
291 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
292 ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */
293 ALTERNATE_FUNCTIONS(16, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 7 reserved */
295 * pins 17 to 20 are special case, only bit 0 is used to select
299 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
300 ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
301 ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
302 ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
303 ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21, bit 4 reserved */
304 ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22, bit 5 reserved */
305 ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23, bit 6 reserved */
306 ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24, bit 7 reserved */
308 ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25, bit 0 reserved */
309 ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26, bit 1 reserved */
310 ALTERNATE_FUNCTIONS(27, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO27, bit 2 reserved */
311 ALTERNATE_FUNCTIONS(28, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO28, bit 3 reserved */
312 ALTERNATE_FUNCTIONS(29, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO29, bit 4 reserved */
313 ALTERNATE_FUNCTIONS(30, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO30, bit 5 reserved */
314 ALTERNATE_FUNCTIONS(31, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO31, bit 6 reserved */
315 ALTERNATE_FUNCTIONS(32, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO32, bit 7 reserved */
317 ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33, bit 0 reserved */
318 ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
319 ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35, bit 2 reserved */
320 ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36, bit 2 reserved */
321 ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37, bit 2 reserved */
322 ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38, bit 2 reserved */
323 ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39, bit 2 reserved */
324 ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7*/
326 ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
327 ALTERNATE_FUNCTIONS(42, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO42, bit 1 reserved */
328 ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43, bit 2 reserved */
329 ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44, bit 3 reserved */
330 ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45, bit 4 reserved */
331 ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46, bit 5 reserved */
332 ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47, bit 6 reserved */
333 ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48, bit 7 reserved */
335 ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */
336 ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA controlled by bit 1 */
337 ALTERNATE_FUNCTIONS(51, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */
338 ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
339 ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
H A Dpinctrl-ab8540.c295 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
304 /* GPIOSEL1 - bit 4-7 reserved */
306 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
307 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
308 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
309 ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
314 /* GPIOSEL2 - bit 0-4 reserved */
320 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
321 ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
322 ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
323 /* GPIOSEL3 - bit 4-7 reserved */
324 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
325 ALTERNATE_FUNCTIONS(18, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */
326 ALTERNATE_FUNCTIONS(19, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */
327 ALTERNATE_FUNCTIONS(20, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */
332 /* GPIOSEL4 - bit 0-1 reserved */
335 ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
336 ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
337 ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
338 ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
339 ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
340 ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
341 /* GPIOSEL5 - bit 0-7 reserved */
350 /* GPIOSEL6 - bit 0 reserved */
352 ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
353 ALTERNATE_FUNCTIONS(43, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */
354 ALTERNATE_FUNCTIONS(44, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */
355 ALTERNATE_FUNCTIONS(45, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */
356 ALTERNATE_FUNCTIONS(46, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */
357 ALTERNATE_FUNCTIONS(47, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */
358 ALTERNATE_FUNCTIONS(48, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */
359 /* GPIOSEL7 - bit 0-1 reserved */
362 ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
363 ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
364 ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
365 ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */
366 ALTERNATE_FUNCTIONS(55, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */
367 ALTERNATE_FUNCTIONS(56, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */
/linux-4.1.27/drivers/net/wireless/zd1211rw/
H A Dzd_rf_rf2959.c51 static int bit(u32 rw, int bit)
53 return bits(rw, bit, bit);
66 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
67 bit(rw, 0));
73 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
74 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
92 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
93 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
116 bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
117 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
118 bit(rw, 1), bit(rw, 0));
134 bit(rw, 17), bit(rw, 16), bit(rw, 15),
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
H A Dopcode_helper.c4 * Helper for the SH-2A 32-bit opcodes.
16 * introduces some 32-bit instructions. Since there are no real
18 * to check the instruction encoding to work out if it's a true 32-bit
21 * Presently, 32-bit opcodes have only slight variations in what the
23 * makes it fairly straightforward to differentiate from the 16-bit ones.
43 case 0x3001: /* 32-bit mov/fmov/movu variants */ instruction_size()
49 case 0x3009: /* 32-bit b*.b bit operations */ instruction_size()
/linux-4.1.27/arch/parisc/include/asm/
H A Dcompat_ucontext.h6 /* 32-bit ucontext as seen from an 64-bit kernel */
/linux-4.1.27/arch/powerpc/mm/
H A Dvphn.h4 /* The H_HOME_NODE_ASSOCIATIVITY h_call returns 6 64-bit registers.
9 * 6 64-bit registers unpacked into up to 24 be32 associativity values. To
/linux-4.1.27/fs/ntfs/
H A Dbitmap.h38 * @start_bit: first bit to set
42 * Set @count bits starting at bit @start_bit in the bitmap described by the
57 * @start_bit: first bit to set
60 * Set @count bits starting at bit @start_bit in the bitmap described by the
74 * @start_bit: first bit to clear
77 * Clear @count bits starting at bit @start_bit in the bitmap described by the
89 * ntfs_bitmap_set_bit - set a bit in a bitmap
91 * @bit: bit to set
93 * Set bit @bit in the bitmap described by the vfs inode @vi.
97 static inline int ntfs_bitmap_set_bit(struct inode *vi, const s64 bit) ntfs_bitmap_set_bit() argument
99 return ntfs_bitmap_set_run(vi, bit, 1); ntfs_bitmap_set_bit()
103 * ntfs_bitmap_clear_bit - clear a bit in a bitmap
105 * @bit: bit to clear
107 * Clear bit @bit in the bitmap described by the vfs inode @vi.
111 static inline int ntfs_bitmap_clear_bit(struct inode *vi, const s64 bit) ntfs_bitmap_clear_bit() argument
113 return ntfs_bitmap_clear_run(vi, bit, 1); ntfs_bitmap_clear_bit()
/linux-4.1.27/include/media/davinci/
H A Dvpfe_types.h29 /* BT656 - 8 bit */
31 /* BT1120 - 16 bit */
35 /* YCbCr - 8 bit with external sync */
37 /* YCbCr - 16 bit with external sync */
39 /* BT656 - 10 bit */
/linux-4.1.27/arch/score/include/asm/
H A Dscoreregs.h15 /* bit 0 Timer enable */
19 /* bit 1 Interrupt enable */
23 /* bit 2 Output enable */
39 /* bit 8..9 External input active edge selection */
44 /* bit 10..11 Operating mode */
/linux-4.1.27/arch/mips/include/uapi/asm/
H A Dptrace.h29 * format is the same for both 32- and 64-bit processes. Registers for 32-bit
62 /* Calls to trace a 64bit program from a 32bit program. */
79 * bit 0 -- 1 if W bit is usable.
80 * bit 1 -- 1 if R bit is usable.
81 * bit 2 -- 1 if I bit is usable.
/linux-4.1.27/arch/ia64/lib/
H A Dchecksum.c21 /* add up 32-bit words for 33 bits */ from64to16()
23 /* add up 16-bit and 17-bit words for 17+c bits */ from64to16()
25 /* add up 16-bit and 2-bit for 16+c bit */ from64to16()
34 * returns a 16-bit checksum, already complemented.
69 * and adds in "sum" (32-bit)
71 * returns a 32-bit number suitable for feeding into itself
77 * it's best to have buff aligned on a 32-bit boundary
H A Dcsum_partial_copy.c22 /* add up 32-bit words for 33 bits */ from64to16()
24 /* add up 16-bit and 17-bit words for 17+c bits */ from64to16()
26 /* add up 16-bit and 2-bit for 16+c bit */ from64to16()
47 count = len >> 1; /* nr of 16-bit words.. */ do_csum_c()
55 count >>= 1; /* nr of 32-bit words.. */ do_csum_c()
63 count >>= 1; /* nr of 64-bit words.. */ do_csum_c()
/linux-4.1.27/arch/s390/kernel/
H A Dmodule.c64 case R_390_GOT12: /* 12 bit GOT offset. */ check_rela()
65 case R_390_GOT16: /* 16 bit GOT offset. */ check_rela()
66 case R_390_GOT20: /* 20 bit GOT offset. */ check_rela()
67 case R_390_GOT32: /* 32 bit GOT offset. */ check_rela()
68 case R_390_GOT64: /* 64 bit GOT offset. */ check_rela()
69 case R_390_GOTENT: /* 32 bit PC rel. to GOT entry shifted by 1. */ check_rela()
70 case R_390_GOTPLT12: /* 12 bit offset to jump slot. */ check_rela()
71 case R_390_GOTPLT16: /* 16 bit offset to jump slot. */ check_rela()
72 case R_390_GOTPLT20: /* 20 bit offset to jump slot. */ check_rela()
73 case R_390_GOTPLT32: /* 32 bit offset to jump slot. */ check_rela()
74 case R_390_GOTPLT64: /* 64 bit offset to jump slot. */ check_rela()
75 case R_390_GOTPLTENT: /* 32 bit rel. offset to jump slot >> 1. */ check_rela()
81 case R_390_PLT16DBL: /* 16 bit PC rel. PLT shifted by 1. */ check_rela()
82 case R_390_PLT32DBL: /* 32 bit PC rel. PLT shifted by 1. */ check_rela()
83 case R_390_PLT32: /* 32 bit PC relative PLT address. */ check_rela()
84 case R_390_PLT64: /* 64 bit PC relative PLT address. */ check_rela()
85 case R_390_PLTOFF16: /* 16 bit offset from GOT to PLT. */ check_rela()
86 case R_390_PLTOFF32: /* 32 bit offset from GOT to PLT. */ check_rela()
87 case R_390_PLTOFF64: /* 16 bit offset from GOT to PLT. */ check_rela()
230 case R_390_8: /* Direct 8 bit. */ apply_rela()
231 case R_390_12: /* Direct 12 bit. */ apply_rela()
232 case R_390_16: /* Direct 16 bit. */ apply_rela()
233 case R_390_20: /* Direct 20 bit. */ apply_rela()
234 case R_390_32: /* Direct 32 bit. */ apply_rela()
235 case R_390_64: /* Direct 64 bit. */ apply_rela()
250 case R_390_PC16: /* PC relative 16 bit. */ apply_rela()
251 case R_390_PC16DBL: /* PC relative 16 bit shifted by 1. */ apply_rela()
252 case R_390_PC32DBL: /* PC relative 32 bit shifted by 1. */ apply_rela()
253 case R_390_PC32: /* PC relative 32 bit. */ apply_rela()
254 case R_390_PC64: /* PC relative 64 bit. */ apply_rela()
267 case R_390_GOT12: /* 12 bit GOT offset. */ apply_rela()
268 case R_390_GOT16: /* 16 bit GOT offset. */ apply_rela()
269 case R_390_GOT20: /* 20 bit GOT offset. */ apply_rela()
270 case R_390_GOT32: /* 32 bit GOT offset. */ apply_rela()
271 case R_390_GOT64: /* 64 bit GOT offset. */ apply_rela()
272 case R_390_GOTENT: /* 32 bit PC rel. to GOT entry shifted by 1. */ apply_rela()
273 case R_390_GOTPLT12: /* 12 bit offset to jump slot. */ apply_rela()
274 case R_390_GOTPLT20: /* 20 bit offset to jump slot. */ apply_rela()
275 case R_390_GOTPLT16: /* 16 bit offset to jump slot. */ apply_rela()
276 case R_390_GOTPLT32: /* 32 bit offset to jump slot. */ apply_rela()
277 case R_390_GOTPLT64: /* 64 bit offset to jump slot. */ apply_rela()
278 case R_390_GOTPLTENT: /* 32 bit rel. offset to jump slot >> 1. */ apply_rela()
309 case R_390_PLT16DBL: /* 16 bit PC rel. PLT shifted by 1. */ apply_rela()
310 case R_390_PLT32DBL: /* 32 bit PC rel. PLT shifted by 1. */ apply_rela()
311 case R_390_PLT32: /* 32 bit PC relative PLT address. */ apply_rela()
312 case R_390_PLT64: /* 64 bit PC relative PLT address. */ apply_rela()
313 case R_390_PLTOFF16: /* 16 bit offset from GOT to PLT. */ apply_rela()
314 case R_390_PLTOFF32: /* 32 bit offset from GOT to PLT. */ apply_rela()
315 case R_390_PLTOFF64: /* 16 bit offset from GOT to PLT. */ apply_rela()
355 case R_390_GOTOFF16: /* 16 bit offset to GOT. */ apply_rela()
356 case R_390_GOTOFF32: /* 32 bit offset to GOT. */ apply_rela()
357 case R_390_GOTOFF64: /* 64 bit offset to GOT. */ apply_rela()
367 case R_390_GOTPC: /* 32 bit PC relative offset to GOT. */ apply_rela()
368 case R_390_GOTPCDBL: /* 32 bit PC rel. off. to GOT shifted by 1. */ apply_rela()
/linux-4.1.27/arch/mips/alchemy/common/
H A Dirq.c290 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au1x_ic0_unmask() local
293 __raw_writel(1 << bit, base + IC_MASKSET); au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); au1x_ic0_unmask()
300 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au1x_ic1_unmask() local
303 __raw_writel(1 << bit, base + IC_MASKSET); au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); au1x_ic1_unmask()
310 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au1x_ic0_mask() local
313 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic0_mask()
320 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au1x_ic1_mask() local
323 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic1_mask()
330 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au1x_ic0_ack() local
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic0_ack()
344 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au1x_ic1_ack() local
351 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic1_ack()
352 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic1_ack()
358 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au1x_ic0_maskack() local
361 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic0_maskack()
362 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic0_maskack()
363 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic0_maskack()
364 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic0_maskack()
370 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au1x_ic1_maskack() local
373 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic1_maskack()
374 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic1_maskack()
375 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic1_maskack()
376 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic1_maskack()
382 int bit = d->irq - AU1000_INTC1_INT_BASE; au1x_ic1_setwake() local
388 if ((bit < 0) || (bit > 7)) au1x_ic1_setwake()
394 wakemsk |= 1 << bit; au1x_ic1_setwake()
396 wakemsk &= ~(1 << bit); au1x_ic1_setwake()
429 unsigned int bit, irq = d->irq; au1x_ic_settype() local
436 bit = irq - AU1000_INTC1_INT_BASE; au1x_ic_settype()
440 bit = irq - AU1000_INTC0_INT_BASE; au1x_ic_settype()
445 if (bit > 31) au1x_ic_settype()
452 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
453 __raw_writel(1 << bit, base + IC_CFG1CLR); au1x_ic_settype()
454 __raw_writel(1 << bit, base + IC_CFG0SET); au1x_ic_settype()
459 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
460 __raw_writel(1 << bit, base + IC_CFG1SET); au1x_ic_settype()
461 __raw_writel(1 << bit, base + IC_CFG0CLR); au1x_ic_settype()
466 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
467 __raw_writel(1 << bit, base + IC_CFG1SET); au1x_ic_settype()
468 __raw_writel(1 << bit, base + IC_CFG0SET); au1x_ic_settype()
473 __raw_writel(1 << bit, base + IC_CFG2SET); au1x_ic_settype()
474 __raw_writel(1 << bit, base + IC_CFG1CLR); au1x_ic_settype()
475 __raw_writel(1 << bit, base + IC_CFG0SET); au1x_ic_settype()
480 __raw_writel(1 << bit, base + IC_CFG2SET); au1x_ic_settype()
481 __raw_writel(1 << bit, base + IC_CFG1SET); au1x_ic_settype()
482 __raw_writel(1 << bit, base + IC_CFG0CLR); au1x_ic_settype()
487 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
488 __raw_writel(1 << bit, base + IC_CFG1CLR); au1x_ic_settype()
489 __raw_writel(1 << bit, base + IC_CFG0CLR); au1x_ic_settype()
552 unsigned long bit; au1300_pinfunc_to_dev() local
555 bit = GPIC_GPIO_TO_BIT(gpio); au1300_pinfunc_to_dev()
556 __raw_writel(bit, r + AU1300_GPIC_DEVSEL); au1300_pinfunc_to_dev()
603 unsigned long bit, irq = d->irq; au1300_gpic_mask() local
607 bit = GPIC_GPIO_TO_BIT(irq); au1300_gpic_mask()
608 __raw_writel(bit, r + AU1300_GPIC_IDIS); au1300_gpic_mask()
617 unsigned long bit, irq = d->irq; au1300_gpic_unmask() local
624 bit = GPIC_GPIO_TO_BIT(irq); au1300_gpic_unmask()
625 __raw_writel(bit, r + AU1300_GPIC_IEN); au1300_gpic_unmask()
632 unsigned long bit, irq = d->irq; au1300_gpic_maskack() local
636 bit = GPIC_GPIO_TO_BIT(irq); au1300_gpic_maskack()
637 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ au1300_gpic_maskack()
638 __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */ au1300_gpic_maskack()
647 unsigned long bit, irq = d->irq; au1300_gpic_ack() local
651 bit = GPIC_GPIO_TO_BIT(irq); au1300_gpic_ack()
652 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ au1300_gpic_ack()
878 unsigned int bit, irq_nr; au1000_init_irq() local
904 bit = irq_nr - AU1000_INTC1_INT_BASE; au1000_init_irq()
907 bit = irq_nr - AU1000_INTC0_INT_BASE; au1000_init_irq()
911 __raw_writel(1 << bit, base + IC_ASSIGNSET); au1000_init_irq()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dipic.c41 .bit = 16,
48 .bit = 17,
55 .bit = 18,
62 .bit = 19,
69 .bit = 20,
76 .bit = 21,
83 .bit = 22,
90 .bit = 23,
97 .bit = 24,
104 .bit = 25,
111 .bit = 26,
118 .bit = 27,
125 .bit = 28,
132 .bit = 29,
139 .bit = 30,
146 .bit = 31,
154 .bit = 1,
162 .bit = 2,
170 .bit = 3,
178 .bit = 4,
186 .bit = 5,
194 .bit = 6,
202 .bit = 7,
209 .bit = 0,
216 .bit = 1,
223 .bit = 2,
230 .bit = 3,
237 .bit = 4,
244 .bit = 5,
251 .bit = 6,
258 .bit = 7,
265 .bit = 8,
272 .bit = 9,
279 .bit = 10,
286 .bit = 11,
293 .bit = 12,
300 .bit = 13,
307 .bit = 14,
314 .bit = 15,
321 .bit = 0,
328 .bit = 0,
335 .bit = 1,
342 .bit = 2,
349 .bit = 3,
356 .bit = 4,
363 .bit = 5,
370 .bit = 6,
377 .bit = 7,
384 .bit = 8,
390 .bit = 9,
396 .bit = 10,
402 .bit = 11,
408 .bit = 12,
414 .bit = 13,
420 .bit = 14,
426 .bit = 15,
432 .bit = 16,
438 .bit = 17,
444 .bit = 18,
450 .bit = 19,
456 .bit = 20,
462 .bit = 21,
468 .bit = 22,
474 .bit = 23,
480 .bit = 24,
486 .bit = 25,
492 .bit = 26,
498 .bit = 27,
504 .bit = 30,
533 temp |= (1 << (31 - ipic_info[src].bit)); ipic_unmask_irq()
549 temp &= ~(1 << (31 - ipic_info[src].bit)); ipic_mask_irq()
568 temp = 1 << (31 - ipic_info[src].bit); ipic_ack_irq()
588 temp &= ~(1 << (31 - ipic_info[src].bit)); ipic_mask_irq_and_ack()
591 temp = 1 << (31 - ipic_info[src].bit); ipic_mask_irq_and_ack()
/linux-4.1.27/drivers/media/tuners/
H A Dtda9887.c62 #define cVideoTrapBypassOFF 0x00 // bit b0
63 #define cVideoTrapBypassON 0x01 // bit b0
65 #define cAutoMuteFmInactive 0x00 // bit b1
66 #define cAutoMuteFmActive 0x02 // bit b1
68 #define cIntercarrier 0x00 // bit b2
69 #define cQSS 0x04 // bit b2
71 #define cPositiveAmTV 0x00 // bit b3:4
72 #define cFmRadio 0x08 // bit b3:4
73 #define cNegativeFmTV 0x10 // bit b3:4
76 #define cForcedMuteAudioON 0x20 // bit b5
77 #define cForcedMuteAudioOFF 0x00 // bit b5
79 #define cOutputPort1Active 0x00 // bit b6
80 #define cOutputPort1Inactive 0x40 // bit b6
82 #define cOutputPort2Active 0x00 // bit b7
83 #define cOutputPort2Inactive 0x80 // bit b7
87 #define cDeemphasisOFF 0x00 // bit c5
88 #define cDeemphasisON 0x20 // bit c5
90 #define cDeemphasis75 0x00 // bit c6
91 #define cDeemphasis50 0x40 // bit c6
93 #define cAudioGain0 0x00 // bit c7
94 #define cAudioGain6 0x80 // bit c7
96 #define cTopMask 0x1f // bit c0:4
97 #define cTopDefault 0x10 // bit c0:4
100 #define cAudioIF_4_5 0x00 // bit e0:1
101 #define cAudioIF_5_5 0x01 // bit e0:1
102 #define cAudioIF_6_0 0x02 // bit e0:1
103 #define cAudioIF_6_5 0x03 // bit e0:1
106 #define cVideoIFMask 0x1c // bit e2:4
107 /* Video IF selection in TV Mode (bit B3=0) */
108 #define cVideoIF_58_75 0x00 // bit e2:4
109 #define cVideoIF_45_75 0x04 // bit e2:4
110 #define cVideoIF_38_90 0x08 // bit e2:4
111 #define cVideoIF_38_00 0x0C // bit e2:4
112 #define cVideoIF_33_90 0x10 // bit e2:4
113 #define cVideoIF_33_40 0x14 // bit e2:4
114 #define cRadioIF_45_75 0x18 // bit e2:4
115 #define cRadioIF_38_90 0x1C // bit e2:4
117 /* IF1 selection in Radio Mode (bit B3=1) */
118 #define cRadioIF_33_30 0x00 // bit e2,4 (also 0x10,0x14)
119 #define cRadioIF_41_30 0x04 // bit e2,4
121 /* Output of AFC pin in radio mode when bit E7=1 */
122 #define cRadioAGC_SIF 0x00 // bit e3
123 #define cRadioAGC_FM 0x08 // bit e3
125 #define cTunerGainNormal 0x00 // bit e5
126 #define cTunerGainLow 0x20 // bit e5
128 #define cGating_18 0x00 // bit e6
129 #define cGating_36 0x40 // bit e6
131 #define cAgcOutON 0x80 // bit e7
132 #define cAgcOutOFF 0x00 // bit e7
556 By default they are set to inactive (bit value 1) by this driver, tda9887_configure()
/linux-4.1.27/drivers/auxdisplay/
H A Dks0108.c64 * There are not bit definitions because they are not flags,
73 #define bit(n) (((unsigned char)1)<<(n)) macro
83 parport_write_control(ks0108_parport, byte ^ (bit(0) | bit(1) | bit(3))); ks0108_writecontrol()
88 ks0108_writedata((state ? bit(0) : 0) | bit(1) | bit(2) | bit(3) | bit(4) | bit(5)); ks0108_displaystate()
93 ks0108_writedata(min(startline,(unsigned char)63) | bit(6) | bit(7)); ks0108_startline()
98 ks0108_writedata(min(address,(unsigned char)63) | bit(6)); ks0108_address()
103 ks0108_writedata(min(page,(unsigned char)7) | bit(3) | bit(4) | bit(5) | bit(7)); ks0108_page()
/linux-4.1.27/drivers/media/platform/vivid/
H A Dvivid-vbi-gen.c41 unsigned bit = 0; vivid_vbi_gen_wss_raw() local
45 wss_insert(wss + bit, 0x1f1c71c7, 29); bit += 29; vivid_vbi_gen_wss_raw()
46 wss_insert(wss + bit, 0x1e3c1f, 24); bit += 24; vivid_vbi_gen_wss_raw()
49 for (i = 0; i <= 13; i++, bit += 6) vivid_vbi_gen_wss_raw()
50 wss_insert(wss + bit, (wss_data & (1 << i)) ? one : zero, 6); vivid_vbi_gen_wss_raw()
52 for (i = 0, bit = 0; bit < sizeof(wss); bit++) { vivid_vbi_gen_wss_raw()
53 unsigned n = ((bit + 1) * sampling_rate) / rate; vivid_vbi_gen_wss_raw()
56 buf[i++] = wss[bit]; vivid_vbi_gen_wss_raw()
65 unsigned bit = 0; vivid_vbi_gen_teletext_raw() local
69 /* prevents 32 bit overflow */ vivid_vbi_gen_teletext_raw()
72 for (i = 0, bit = 0; bit < sizeof(teletext) * 8; bit++) { vivid_vbi_gen_teletext_raw()
73 unsigned n = ((bit + 1) * sampling_rate) / rate; vivid_vbi_gen_teletext_raw()
74 u8 val = (teletext[bit / 8] & (1 << (bit & 7))) ? 0xc0 : 0x10; vivid_vbi_gen_teletext_raw()
105 /* Start bit of 1 (each bit is two cycles) */ vivid_vbi_gen_cc_raw()
108 unsigned bit, i; vivid_vbi_gen_cc_raw() local
113 for (i = 0, bit = 0; bit < sizeof(cc); bit++) { vivid_vbi_gen_cc_raw()
114 unsigned n = ((bit + 1) * sampling_rate) / rate; vivid_vbi_gen_cc_raw()
117 buf[i++] = cc[bit] ? 0xc0 : 0x10; vivid_vbi_gen_cc_raw()
/linux-4.1.27/arch/ia64/include/asm/
H A Dbitops.h22 * set_bit - Atomically set a bit in memory
23 * @nr: the bit to set
36 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
41 __u32 bit, old, new; set_bit() local
46 bit = 1 << (nr & 31); set_bit()
50 new = old | bit; set_bit()
55 * __set_bit - Set a bit in memory
56 * @nr: the bit to set
70 * clear_bit - Clears a bit in memory
96 * clear_bit_unlock - Clears a bit in memory with release
120 * __clear_bit_unlock - Non-atomically clears a bit in memory with release
137 * __clear_bit - Clears a bit in memory (non-atomic version)
138 * @nr: the bit to clear
152 * change_bit - Toggle a bit in memory
163 __u32 bit, old, new; change_bit() local
168 bit = (1 << (nr & 31)); change_bit()
172 new = old ^ bit; change_bit()
177 * __change_bit - Toggle a bit in memory
178 * @nr: the bit to toggle
192 * test_and_set_bit - Set a bit and return its old value
202 __u32 bit, old, new; test_and_set_bit() local
207 bit = 1 << (nr & 31); test_and_set_bit()
211 new = old | bit; test_and_set_bit()
213 return (old & bit) != 0; test_and_set_bit()
217 * test_and_set_bit_lock - Set a bit and return its old value for lock
226 * __test_and_set_bit - Set a bit and return its old value
246 * test_and_clear_bit - Clear a bit and return its old value
271 * __test_and_clear_bit - Clear a bit and return its old value
291 * test_and_change_bit - Change a bit and return its old value
301 __u32 bit, old, new; test_and_change_bit() local
306 bit = (1 << (nr & 31)); test_and_change_bit()
310 new = old ^ bit; test_and_change_bit()
312 return (old & bit) != 0; test_and_change_bit()
316 * __test_and_change_bit - Change a bit and return its old value
325 __u32 old, bit = (1 << (nr & 31)); __test_and_change_bit() local
329 *m = old ^ bit; __test_and_change_bit()
330 return (old & bit) != 0; __test_and_change_bit()
340 * ffz - find the first zero bit in a long word
341 * @x: The long word to find the bit in
343 * Returns the bit-number (0..63) of the first (least significant) zero bit.
356 * __ffs - find first bit in word.
359 * Undefined if no bit exists, so code should check against 0 first.
373 * Return bit number of last (most-significant) bit set. Undefined
387 * Find the last (most significant) bit set. Returns 0 for x==0 and
406 * Find the last (most significant) bit set. Undefined for x==0.
427 * of bits set) of a N-bit word
/linux-4.1.27/drivers/net/wireless/brcm80211/include/
H A Dbrcmu_d11.h31 /* bit 0~7 channel number
32 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
41 /* bit 8~16 for dot 11n IO types
42 * bit 8~9 sideband
43 * bit 10~11 bandwidth
44 * bit 12~13 spectral band
45 * bit 14~15 not used
62 /* bit 8~16 for dot 11ac IO types
63 * bit 8~10 sideband
64 * bit 11~13 bandwidth
65 * bit 14~15 spectral band
/linux-4.1.27/arch/x86/platform/efi/
H A Defi_thunk_64.S4 * Support for invoking 32-bit EFI runtime services from a 64-bit
10 * intact (GDT, IDT, etc) and simply invoke the the 32-bit EFI runtime
15 * 64-bit virtual address space. Things like the stack and instruction
16 * addresses need to be accessible by the 32-bit firmware, so we rely on
32 * Switch to 1:1 mapped 32-bit stack pointer.
46 * 64-bit values. Note that all the addresses on the stack are
47 * 32-bit.
89 /* Switch to 32-bit descriptor */
105 * Convert 32-bit status code into 64-bit.
129 * The stack should represent the 32-bit calling convention.
/linux-4.1.27/arch/parisc/include/uapi/asm/
H A Dipcbuf.h6 * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the kernel.
8 * on 64-bit kernels as on 32-bit ones.
/linux-4.1.27/drivers/gpio/
H A Dgpio-sta2x11.c79 u32 bit = __bit(nr); gsta_gpio_set() local
82 writel(bit, &regs->dats); gsta_gpio_set()
84 writel(bit, &regs->datc); gsta_gpio_set()
91 u32 bit = __bit(nr); gsta_gpio_get() local
93 return readl(&regs->dat) & bit; gsta_gpio_get()
101 u32 bit = __bit(nr); gsta_gpio_direction_output() local
103 writel(bit, &regs->dirs); gsta_gpio_direction_output()
106 writel(bit, &regs->dats); gsta_gpio_direction_output()
108 writel(bit, &regs->datc); gsta_gpio_direction_output()
116 u32 bit = __bit(nr); gsta_gpio_direction_input() local
118 writel(bit, &regs->dirc); gsta_gpio_direction_input()
170 u32 bit = __bit(nr); gsta_set_config() local
183 val |= bit; gsta_set_config()
185 val &= ~bit; gsta_set_config()
186 writel(val | bit, &regs->afsela); gsta_set_config()
195 writel(bit, &regs->dirs); gsta_set_config()
196 writel(bit, &regs->datc); gsta_set_config()
199 writel(bit, &regs->dirs); gsta_set_config()
200 writel(bit, &regs->dats); gsta_set_config()
203 writel(bit, &regs->dirc); gsta_set_config()
204 val = readl(&regs->pdis) | bit; gsta_set_config()
208 writel(bit, &regs->dirc); gsta_set_config()
209 val = readl(&regs->pdis) & ~bit; gsta_set_config()
211 writel(bit, &regs->dats); gsta_set_config()
214 writel(bit, &regs->dirc); gsta_set_config()
215 val = readl(&regs->pdis) & ~bit; gsta_set_config()
217 writel(bit, &regs->datc); gsta_set_config()
238 u32 bit = __bit(nr); gsta_irq_disable() local
244 val = readl(&regs->rimsc) & ~bit; gsta_irq_disable()
248 val = readl(&regs->fimsc) & ~bit; gsta_irq_disable()
261 u32 bit = __bit(nr); gsta_irq_enable() local
271 writel(val | bit, &regs->rimsc); gsta_irq_enable()
273 writel(val & ~bit, &regs->rimsc); gsta_irq_enable()
276 writel(val | bit, &regs->fimsc); gsta_irq_enable()
278 writel(val & ~bit, &regs->fimsc); gsta_irq_enable()
H A Dgpio-it8761e.c81 u8 bit; it8761e_gpio_get() local
83 bit = gpio_num % 8; it8761e_gpio_get()
86 return !!(inb(reg) & (1 << bit)); it8761e_gpio_get()
92 u8 io_reg, bit; it8761e_gpio_direction_in() local
94 bit = gpio_num % 8; it8761e_gpio_direction_in()
104 if (curr_dirs & (1 << bit)) it8761e_gpio_direction_in()
105 write_reg(curr_dirs & ~(1 << bit), io_reg, port); it8761e_gpio_direction_in()
116 u8 curr_vals, bit; it8761e_gpio_set() local
119 bit = gpio_num % 8; it8761e_gpio_set()
126 outb(curr_vals | (1 << bit) , reg); it8761e_gpio_set()
128 outb(curr_vals & ~(1 << bit), reg); it8761e_gpio_set()
136 u8 curr_dirs, io_reg, bit; it8761e_gpio_direction_out() local
138 bit = gpio_num % 8; it8761e_gpio_direction_out()
150 if (!(curr_dirs & (1 << bit))) it8761e_gpio_direction_out()
151 write_reg(curr_dirs | (1 << bit), io_reg, port); it8761e_gpio_direction_out()
H A Dgpio-mc9s08dz60.c38 static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit) mc9s_gpio_to_reg_and_bit() argument
41 *bit = offset % GPIO_NUM_PER_GROUP; mc9s_gpio_to_reg_and_bit()
46 u8 reg, bit; mc9s08dz60_get_value() local
50 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit); mc9s08dz60_get_value()
53 return (value >= 0) ? (value >> bit) & 0x1 : 0; mc9s08dz60_get_value()
58 u8 reg, bit; mc9s08dz60_set() local
61 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit); mc9s08dz60_set()
65 value |= 1 << bit; mc9s08dz60_set()
67 value &= ~(1 << bit); mc9s08dz60_set()
/linux-4.1.27/arch/frv/include/asm/
H A Dbitops.h1 /* bitops.h: bit operations for the Fujitsu FR-V CPUs
241 * fls - find last bit set
245 * - return 32..1 to indicate bit 31..0 most significant bit set
250 int bit; \
257 : "=&r"(bit) \
262 bit; \
266 * fls64 - find last bit set in a 64-bit value
270 * - return 64..1 to indicate bit 63..0 most significant bit set
280 int bit, x, y; fls64() local
298 : "=&r"(bit), "=r"(x), "=r"(y) fls64()
302 return bit; fls64()
307 * ffs - find first bit set
310 * - return 32..1 to indicate bit 31..0 most least significant bit set
317 * (rightmost) 1-bit of the value in x. ffs()
323 * __ffs - find first bit set
326 * - return 31..0 to indicate bit 31..0 most least significant bit set
332 int bit; __ffs() local
333 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x)); __ffs()
334 return 31 - bit; __ffs()
338 * __fls - find last (most-significant) set bit in a long word
341 * Undefined if no set bit exists, so code should check against 0 first.
345 unsigned long bit; __fls() local
346 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word)); __fls()
347 return bit; __fls()
358 int bit; __ilog2_u32() local
359 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n)); __ilog2_u32()
360 return 31 - bit; __ilog2_u32()
375 int bit, x, y; __ilog2_u64() local
387 : "=&r"(bit), "=r"(x), "=r"(y) __ilog2_u64()
391 return bit; __ilog2_u64()
/linux-4.1.27/arch/mips/include/asm/
H A Dbitops.h59 * set_bit - Atomically set a bit in memory
60 * @nr: the bit to set
71 int bit = nr & SZLONG_MASK; set_bit() local
83 : "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m)); set_bit()
85 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { set_bit()
92 : "ir" (bit), "r" (~0)); set_bit()
104 : "ir" (1UL << bit)); set_bit()
111 * clear_bit - Clears a bit in memory
123 int bit = nr & SZLONG_MASK; clear_bit() local
135 : "ir" (~(1UL << bit))); clear_bit()
137 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { clear_bit()
144 : "ir" (bit)); clear_bit()
156 : "ir" (~(1UL << bit))); clear_bit()
163 * clear_bit_unlock - Clears a bit in memory
177 * change_bit - Toggle a bit in memory
187 int bit = nr & SZLONG_MASK; change_bit() local
201 : "ir" (1UL << bit)); change_bit()
214 : "ir" (1UL << bit)); change_bit()
221 * test_and_set_bit - Set a bit and return its old value
231 int bit = nr & SZLONG_MASK; test_and_set_bit() local
249 : "r" (1UL << bit) test_and_set_bit()
263 : "r" (1UL << bit) test_and_set_bit()
267 res = temp & (1UL << bit); test_and_set_bit()
277 * test_and_set_bit_lock - Set a bit and return its old value
287 int bit = nr & SZLONG_MASK; test_and_set_bit_lock() local
303 : "r" (1UL << bit) test_and_set_bit_lock()
317 : "r" (1UL << bit) test_and_set_bit_lock()
321 res = temp & (1UL << bit); test_and_set_bit_lock()
330 * test_and_clear_bit - Clear a bit and return its old value
340 int bit = nr & SZLONG_MASK; test_and_clear_bit() local
359 : "r" (1UL << bit) test_and_clear_bit()
373 : "ir" (bit) test_and_clear_bit()
390 : "r" (1UL << bit) test_and_clear_bit()
394 res = temp & (1UL << bit); test_and_clear_bit()
404 * test_and_change_bit - Change a bit and return its old value
414 int bit = nr & SZLONG_MASK; test_and_change_bit() local
432 : "r" (1UL << bit) test_and_change_bit()
446 : "r" (1UL << bit) test_and_change_bit()
450 res = temp & (1UL << bit); test_and_change_bit()
462 * __clear_bit_unlock - Clears a bit in memory
477 * Return the bit position (0..63) of the most significant 1 bit in a word
478 * Returns -1 if no 1 bit exists
540 * __ffs - find first bit in word.
544 * Undefined if no bit exists, so code should check against 0 first.
552 * fls - find last bit set.
604 * ffs - find first bit set.
H A Daddrspace.h35 * 32-bit MIPS address spaces
60 * Memory segments (64bit kernel mode addresses)
61 * The compatibility segments use the full 64-bit sign extended value. Note
94 * Memory segments (32bit kernel mode addresses)
95 * These are the traditional names used in the 32-bit universe.
124 * 64-bit address conversions
133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
135 * R8000 implements most with its 48-bit physical address space.
142 * The R8000 doesn't have the 32-bit compat spaces so we don't define them
147 #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
146 * - Step by 8 for 64 bit access.
148 * Note: When performing 32 and 64 bit access, only the low
162 * Perform an atomic 64 bit add
165 * - Step by 8 for 64 bit access.
177 * Perform an atomic 32 bit add
180 * - Step by 4 for 32 bit access.
193 * Perform an atomic 16 bit add
196 * - Step by 2 for 16 bit access.
208 * Perform an atomic 8 bit add
221 * Perform an atomic 64 bit add after the current tag switch
225 * - Step by 8 for 64 bit access.
228 * Returns If a timeout occurs, the error bit will be set. Otherwise
245 * Perform an atomic 32 bit add after the current tag switch
249 * - Step by 4 for 32 bit access.
252 * Returns If a timeout occurs, the error bit will be set. Otherwise
270 * Perform an atomic 16 bit add after the current tag switch
274 * - Step by 2 for 16 bit access.
276 * Returns If a timeout occurs, the error bit will be set. Otherwise
294 * Perform an atomic 8 bit add after the current tag switch
299 * Returns If a timeout occurs, the error bit will be set. Otherwise
320 * Note: When performing 32 and 64 bit access, only the low
332 * - Step by 2 for 16 bit access.
333 * - Step by 4 for 32 bit access.
334 * - Step by 8 for 64 bit access.
352 * Perform an async atomic 64 bit add. The old value is
358 * - Step by 8 for 64 bit access.
372 * Perform an async atomic 32 bit add. The old value is
378 * - Step by 4 for 32 bit access.
392 * Perform an async atomic 16 bit add. The old value is
398 * - Step by 2 for 16 bit access.
411 * Perform an async atomic 8 bit add. The old value is
429 * Perform an async atomic 64 bit add after the current tag
433 * 8 byte aligned. If a timeout occurs, the error bit (63)
438 * - Step by 8 for 64 bit access.
452 * Perform an async atomic 32 bit add after the current tag
456 * 8 byte aligned. If a timeout occurs, the error bit (63)
461 * - Step by 4 for 32 bit access.
475 * Perform an async atomic 16 bit add after the current tag
479 * 8 byte aligned. If a timeout occurs, the error bit (63)
484 * - Step by 2 for 16 bit access.
498 * Perform an async atomic 8 bit add after the current tag
502 * 8 byte aligned. If a timeout occurs, the error bit (63)
520 * Perform an atomic 64 bit add
523 * - Step by 8 for 64 bit access.
532 * Perform an atomic 32 bit add
535 * - Step by 4 for 32 bit access.
545 * Perform an atomic 16 bit add
548 * - Step by 2 for 16 bit access.
558 * Perform an atomic 8 bit add
570 * Perform an atomic 64 bit write
573 * - Step by 8 for 64 bit access.
582 * Perform an atomic 32 bit write
585 * - Step by 4 for 32 bit access.
595 * Perform an atomic 16 bit write
598 * - Step by 2 for 16 bit access.
608 * Perform an atomic 8 bit write
/linux-4.1.27/drivers/input/tablet/
H A Dwacom_serial4.c38 * bit 7 Sync bit always 1
39 * bit 6 Pointing device detected
40 * bit 5 Cursor = 0 / Stylus = 1
41 * bit 4 Reserved
42 * bit 3 1 if a button on the pointing device has been pressed
43 * bit 2 P0 (optional)
44 * bit 1 X15
45 * bit 0 X14
48 * bit 7 Always 0
52 * bit 7 Always 0
56 * bit 7 Always 0
57 * bit 6 B3
58 * bit 5 B2
59 * bit 4 B1
60 * bit 3 B0
61 * bit 2 P1 (optional)
62 * bit 1 Y15
63 * bit 0 Y14
66 * bit 7 Always 0
70 * bit 7 Always 0
74 * bit 7 Always 0
75 * bit 6 Sign of pressure data; or wheel-rel for cursor tool
76 * bit 5 P7; or REL1 for cursor tool
77 * bit 4 P6; or REL0 for cursor tool
78 * bit 3 P5
79 * bit 2 P4
80 * bit 1 P3
81 * bit 0 P2
87 * bit 7 Always 0
88 * bit 6 Sign of tilt X
89 * bit 5 Xt6
90 * bit 4 Xt5
91 * bit 3 Xt4
92 * bit 2 Xt3
93 * bit 1 Xt2
94 * bit 0 Xt1
97 * bit 7 Always 0
98 * bit 6 Sign of tilt Y
99 * bit 5 Yt6
100 * bit 4 Yt5
101 * bit 3 Yt4
102 * bit 2 Yt3
103 * bit 1 Yt2
104 * bit 0 Yt1
/linux-4.1.27/net/llc/
H A Dllc_pdu.c27 * pdu_set_pf_bit - sets poll/final bit in LLC header
28 * @pdu_frame: input frame that p/f bit must be set into it.
29 * @bit_value: poll/final bit (0 or 1).
31 * This function sets poll/final bit in LLC header (based on type of PDU).
32 * in I or S pdus, p/f bit is right bit of fourth byte in header. in U
33 * pdus p/f bit is fifth bit of third byte.
55 * llc_pdu_decode_pf_bit - extracs poll/final bit from LLC header
56 * @skb: input skb that p/f bit must be extracted from it
57 * @pf_bit: poll/final bit (0 or 1)
59 * This function extracts poll/final bit from LLC header (based on type of
60 * PDU). In I or S pdus, p/f bit is right bit of fourth byte in header. In
61 * U pdus p/f bit is fifth bit of third byte.
85 * @p_bit: The P bit to set in the PDU
101 * @p_bit: The P bit to set in the PDU
113 pdu->ctrl_2 |= (p_bit & LLC_I_PF_BIT_MASK); /* p/f bit */ llc_pdu_init_as_i_cmd()
121 * @p_bit: The P bit to set in the PDU
141 * @p_bit: The P bit to set in the PDU
161 * @p_bit: The P bit to set in the PDU
180 * @p_bit: The P bit to set in the PDU
196 * @f_bit: The F bit to set in the PDU
213 * @f_bit: The F bit to set in the PDU
250 * @f_bit: The F bit to set in the PDU
270 * @f_bit: The F bit to set in the PDU
290 * @f_bit: The F bit to set in the PDU
310 * @f_bit: The F bit to set in the PDU
344 * llc_pdu_get_pf_bit - extracts p/f bit of input PDU
347 * This function extracts p/f bit of input PDU. at first examines type of
348 * PDU and then extracts p/f bit. Returns the p/f bit.
/linux-4.1.27/drivers/scsi/pcmcia/
H A DMakefile4 # 16-bit client drivers
/linux-4.1.27/arch/sparc/include/asm/
H A Dhardirq_32.h1 /* hardirq.h: 32-bit Sparc hard IRQ support.
H A Dhardirq_64.h1 /* hardirq.h: 64-bit Sparc hard IRQ support.
/linux-4.1.27/arch/metag/lib/
H A Dmodsi3.S7 !! 32-bit modulus unsigned i/p - passed unsigned 32-bit numbers
22 !! 32-bit modulus signed i/p - passed signed 32-bit numbers
/linux-4.1.27/drivers/video/fbdev/matrox/
H A Dmatroxfb_maven.h6 #include <linux/i2c-algo-bit.h>
/linux-4.1.27/arch/sh/include/asm/
H A Dromimage-macros.h8 /* The ED command is used to write a 32-bit word */
21 /* The EW command is used to write a 16-bit word */
34 /* The EB command is used to write an 8-bit word */
62 /* The DD command is used to read a 32-bit word */
H A Dpgtable_32.h7 * Hardware and software bit definitions for the PTEL value (see below for
8 * notes on SH-X2 MMUs and 64-bit PTEs):
12 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
13 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
23 * Bit 10 is used for _PAGE_ACCESSED, and bit 11 is used for _PAGE_SPECIAL.
25 * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
26 * and timing control which (together with bit 0) are moved into the
33 * SZ bit placeholders still exist in data array 1, but are implemented as
36 * The downside to this is that we can no longer fit everything in to a 32-bit
37 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
41 #define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
42 #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
43 #define _PAGE_DIRTY 0x004 /* D-bit : page changed */
44 #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
45 #define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
46 #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
47 #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
48 #define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
49 #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
58 #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
59 #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
60 #define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
61 #define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
63 #define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
64 #define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
65 #define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
67 #define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
68 #define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
69 #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
86 #define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
87 #define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
88 #define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
89 #define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
90 #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
91 #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
356 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
358 * kernel permissions), we attempt to couple them a bit more sanely here.
443 * _PAGE_PRESENT at bit 8
444 * _PAGE_PROTNONE at bit 9
447 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
449 * offset (along with a 5-bit type), following the same approach as x86
452 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
453 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
/linux-4.1.27/arch/mips/sibyte/swarm/
H A Drtc_m41t81.c32 #define M41T81REG_SC_ST 0x80 /* stop bit */
33 #define M41T81REG_HR_CB 0x40 /* century bit */
34 #define M41T81REG_HR_CEB 0x80 /* century enable bit */
35 #define M41T81REG_CTL_S 0x20 /* sign bit */
36 #define M41T81REG_CTL_FT 0x40 /* frequency test bit */
38 #define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
39 #define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
40 #define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
41 #define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
42 #define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
43 #define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
44 #define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
45 #define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
48 #define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */
49 #define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */
50 #define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */
51 #define M41T81REG_AHR_HT 0x40 /* halt update bit */
52 #define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */
53 #define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */
56 #define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */
57 #define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */
58 #define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */
59 #define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */
107 /* Clear error bit by writing a 1 */ m41t81_read()
129 /* Clear error bit by writing a 1 */ m41t81_write()
/linux-4.1.27/arch/powerpc/kernel/
H A Dswsusp_64.c2 * PowerPC 64-bit swsusp implementation
/linux-4.1.27/arch/arm/plat-samsung/
H A Dwakeup-mask.c32 val |= mask->bit; samsung_sync_wakemask()
38 /* bit of a liberty to read this directly from irq_data. */ samsung_sync_wakemask()
40 val &= ~mask->bit; samsung_sync_wakemask()
42 val |= mask->bit; samsung_sync_wakemask()
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Darm_timer.h10 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
11 * can have 16-bit or 32-bit selectable via a bit in the control register.
/linux-4.1.27/arch/arm/mach-mmp/include/mach/
H A Dmfp.h7 * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
8 * bit different from those on PXA3xx. Bit [7:10] are now reserved, which
15 * 2. DRIVE strength definitions redefined to include the reserved bit
16 * - the reserved bit differs between pxa168 and pxa910, and the
/linux-4.1.27/lib/mpi/
H A DMakefile16 mpi-bit.o \
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-simtec.c25 #include <linux/i2c-algo-bit.h>
31 struct i2c_algo_bit_data bit; member in struct:simtec_i2c_data
40 /* i2c bit-bus functions */
107 pd->adap.algo_data = &pd->bit; simtec_i2c_probe()
112 pd->bit.data = pd; simtec_i2c_probe()
113 pd->bit.setsda = simtec_i2c_setsda; simtec_i2c_probe()
114 pd->bit.setscl = simtec_i2c_setscl; simtec_i2c_probe()
115 pd->bit.getsda = simtec_i2c_getsda; simtec_i2c_probe()
116 pd->bit.getscl = simtec_i2c_getscl; simtec_i2c_probe()
117 pd->bit.timeout = HZ; simtec_i2c_probe()
118 pd->bit.udelay = 20; simtec_i2c_probe()
/linux-4.1.27/arch/metag/include/uapi/asm/
H A Dptrace.h12 /* CBMarker bit (indicates catch state / catch replay) */
18 /* SCC bit (indicates split 16x16 condition flags) */
23 /* CF_Z bit (Zero flag) */
26 /* CF_N bit (Negative flag) */
29 /* CF_V bit (oVerflow flag) */
32 /* CF_C bit (Carry flag) */
37 /* SCF_LZ bit (Low Zero flag) */
40 /* SCF_HZ bit (High Zero flag) */
43 /* SCF_HC bit (High Carry flag) */
46 /* SCF_LC bit (Low Carry flag) */
59 * @_pad1: Reserved padding to make sizeof obviously 64bit aligned
/linux-4.1.27/drivers/media/pci/cx25821/
H A Dcx25821-gpio.c30 int bit = pin_number; cx25821_set_gpiopin_direction() local
40 bit = pin_number - 31; cx25821_set_gpiopin_direction()
48 value = gpio_register | Set_GPIO_Bit(bit); cx25821_set_gpiopin_direction()
50 value = gpio_register & Clear_GPIO_Bit(bit); cx25821_set_gpiopin_direction()
59 int bit = pin_number; cx25821_set_gpiopin_logicvalue() local
71 bit = pin_number - 31; cx25821_set_gpiopin_logicvalue()
78 value &= Clear_GPIO_Bit(bit); cx25821_set_gpiopin_logicvalue()
80 value |= Set_GPIO_Bit(bit); cx25821_set_gpiopin_logicvalue()
/linux-4.1.27/drivers/staging/android/
H A Dashmem.h21 /* support of 32bit userspace on 64bit platforms */
/linux-4.1.27/arch/s390/include/uapi/asm/
H A Dipcbuf.h10 * - 32-bit mode_t and seq
11 * - 2 miscellaneous 32-bit values
/linux-4.1.27/arch/mn10300/include/uapi/asm/
H A Dsembuf.h10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
/linux-4.1.27/arch/avr32/include/uapi/asm/
H A Dsembuf.h10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
/linux-4.1.27/arch/cris/include/arch-v32/arch/
H A Dchecksum.h8 * generate carry-additions for the 32-bit components of the
10 * 16-bit components and then add.
/linux-4.1.27/arch/cris/include/uapi/asm/
H A Dsembuf.h10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
H A Detraxgpio.h6 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
7 * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
16 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
17 * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
18 * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
19 * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
20 * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
24 * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
25 * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
26 * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
27 * /dev/gpiod minor 4, 32 bit GPIO, input only
123 /* bit set in low byte0 is CLK mask (0x00FF),
124 bit set in byte1 is DATA mask (0xFF00)
132 * 32 bit ports (port G) properly.
/linux-4.1.27/arch/frv/include/uapi/asm/
H A Dsembuf.h10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
/linux-4.1.27/arch/m32r/include/uapi/asm/
H A Dsembuf.h10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
/linux-4.1.27/arch/arm/mach-clps711x/
H A Dcommon.h10 #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
/linux-4.1.27/include/asm-generic/
H A Dchecksum.h6 * and adds in "sum" (32-bit)
8 * returns a 32-bit number suitable for feeding into itself
14 * it's best to have buff aligned on a 32-bit boundary
22 * here even more important to align src and dst on a 32-bit (or even
23 * better 64-bit) boundary
30 * here even more important to align src and dst on a 32-bit (or even
31 * better 64-bit) boundary
65 * returns a 16-bit checksum, already complemented
/linux-4.1.27/drivers/dma/ioat/
H A Dregisters.h30 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
32 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
39 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
42 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
48 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
50 #define IOAT_VER_OFFSET 0x08 /* 8-bit */
56 #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
58 #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
62 #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
68 #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */
84 #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
98 #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
103 #define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
104 #define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
126 #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */
128 #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */
192 #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
193 #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */
205 #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
206 #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */
216 #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
220 #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
224 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
247 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
/linux-4.1.27/arch/x86/math-emu/
H A Dstatus_w.h22 #define SW_C3 Const__(0x4000) /* condition bit 3 */
25 #define SW_C2 Const__(0x0400) /* condition bit 2 */
26 #define SW_C1 Const__(0x0200) /* condition bit 1 */
27 #define SW_C0 Const__(0x0100) /* condition bit 0 */
37 #define SW_Exc_Mask Const__(0x27f) /* Status word exception bit mask */
59 /* Clear the SW_C1 bit, "other bits undefined". */
H A Dwm_shrx.S5 | 64 bit right shift functions |
26 | Shifts the 64 bit quantity pointed to by the first arg (arg1) |
28 | Forms a 96 bit quantity from the 64 bit arg and eax: |
29 | [ 64 bit arg ][ eax ] |
32 | Results returned in the 64 bit arg and eax. |
102 | Shifts the 64 bit quantity pointed to by the first arg (arg1) |
104 | Forms a 96 bit quantity from the 64 bit arg and eax: |
105 | [ 64 bit arg ][ eax ] |
109 | set (to 0x01) if any bit, apart from the first one, is set in the |
111 | Results returned in the 64 bit arg and eax. |
140 orw %bx,%bx /* Any of the 63 bit set ? */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dbit.c25 #include <subdev/bios/bit.h>
28 bit_entry(struct nvkm_bios *bios, u8 id, struct bit_entry *bit) bit_entry() argument
35 bit->id = nv_ro08(bios, entry + 0); bit_entry()
36 bit->version = nv_ro08(bios, entry + 1); bit_entry()
37 bit->length = nv_ro16(bios, entry + 2); bit_entry()
38 bit->offset = nv_ro16(bios, entry + 4); bit_entry()
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Dgpio.h30 * gpiofunc[x]==0 bit = gpio
31 * func[x]==1 bit = altfunc
34 * gpiocfg[x]==0 bit = input
35 * gpiocfg[x]==1 bit = output
86 extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
87 extern void rb532_gpio_set_istat(int bit, unsigned gpio);
/linux-4.1.27/include/linux/spi/
H A Deeprom.h18 #define EE_ADDR1 0x0001 /* 8 bit addrs */
19 #define EE_ADDR2 0x0002 /* 16 bit addrs */
20 #define EE_ADDR3 0x0004 /* 24 bit addrs */
27 * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
28 * is used. This instruction bit is normally defined as don't care for
/linux-4.1.27/arch/parisc/math-emu/
H A Dfcnvxf.c69 * set sign bit of result and get magnitude of source sgl_to_sgl_fcnvxf()
89 * Check word for most significant bit set. Returns sgl_to_sgl_fcnvxf()
90 * a value in dst_exponent indicating the bit position, sgl_to_sgl_fcnvxf()
94 /* left justify source, with msb at bit position 1 */ sgl_to_sgl_fcnvxf()
140 * set sign bit of result and get magnitude of source sgl_to_dbl_fcnvxf()
160 * Check word for most significant bit set. Returns sgl_to_dbl_fcnvxf()
161 * a value in dst_exponent indicating the bit position, sgl_to_dbl_fcnvxf()
165 /* left justify source, with msb at bit position 1 */ sgl_to_dbl_fcnvxf()
191 * set sign bit of result and get magnitude of source dbl_to_sgl_fcnvxf()
212 * Check word for most significant bit set. Returns dbl_to_sgl_fcnvxf()
213 * a value in dst_exponent indicating the bit position, dbl_to_sgl_fcnvxf()
217 /* left justify source, with msb at bit position 1 */ dbl_to_sgl_fcnvxf()
228 * adjust bit position count dbl_to_sgl_fcnvxf()
234 * Check word for most significant bit set. Returns dbl_to_sgl_fcnvxf()
235 * a value in dst_exponent indicating the bit position, dbl_to_sgl_fcnvxf()
240 /* left justify source, with msb at bit position 1 */ dbl_to_sgl_fcnvxf()
296 * set sign bit of result and get magnitude of source dbl_to_dbl_fcnvxf()
317 * Check word for most significant bit set. Returns dbl_to_dbl_fcnvxf()
318 * a value in dst_exponent indicating the bit position, dbl_to_dbl_fcnvxf()
322 /* left justify source, with msb at bit position 1 */ dbl_to_dbl_fcnvxf()
333 * adjust bit position count dbl_to_dbl_fcnvxf()
339 * Check word for most significant bit set. Returns dbl_to_dbl_fcnvxf()
340 * a value in dst_exponent indicating the bit position, dbl_to_dbl_fcnvxf()
344 /* left justify source, with msb at bit position 1 */ dbl_to_dbl_fcnvxf()
/linux-4.1.27/arch/arm/mach-shmobile/include/mach/
H A Dzboot_macros.h8 /* The ED command is used to write a 32-bit word */
19 /* The EW command is used to write a 16-bit word */
30 /* The EB command is used to write an 8-bit word */
57 /* The DD command is used to read a 32-bit word */
82 /* read 32-bit value from addr, "or" an immediate and write back */
95 /* read 32-bit value from addr, "and" an immediate and write back */
/linux-4.1.27/arch/alpha/kernel/
H A Dirq_pyxis.c20 /* Note mask bit is true for ENABLED irqs. */
46 unsigned long bit = 1UL << (d->irq - 16); pyxis_mask_and_ack_irq() local
47 unsigned long mask = cached_irq_mask &= ~bit; pyxis_mask_and_ack_irq()
53 *(vulp)PYXIS_INT_REQ = bit; pyxis_mask_and_ack_irq()
77 * Now for every possible bit set, work through them and call pyxis_device_interrupt()
82 pld &= pld - 1; /* clear least bit set */ pyxis_device_interrupt()
H A Dsys_sable.c39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
93 sable_update_irq_hw(unsigned long bit, unsigned long mask) sable_update_irq_hw() argument
97 if (bit >= 16) { sable_update_irq_hw()
100 } else if (bit >= 8) { sable_update_irq_hw()
109 sable_ack_irq_hw(unsigned long bit) sable_ack_irq_hw() argument
113 if (bit >= 16) { sable_ack_irq_hw()
115 val1 = 0xE0 | (bit - 16); sable_ack_irq_hw()
117 } else if (bit >= 8) { sable_ack_irq_hw()
119 val1 = 0xE0 | (bit - 8); sable_ack_irq_hw()
123 val1 = 0xE0 | (bit - 0); sable_ack_irq_hw()
187 * above for PCI interrupts. The IRQ relates to which bit the interrupt
292 lynx_update_irq_hw(unsigned long bit, unsigned long mask) lynx_update_irq_hw() argument
308 lynx_ack_irq_hw(unsigned long bit) lynx_ack_irq_hw() argument
310 *(vulp)T2_VAR = (u_long) bit; lynx_ack_irq_hw()
447 unsigned long bit, mask; sable_lynx_enable_irq() local
449 bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq]; sable_lynx_enable_irq()
451 mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit); sable_lynx_enable_irq()
452 sable_lynx_irq_swizzle->update_irq_hw(bit, mask); sable_lynx_enable_irq()
455 printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n", sable_lynx_enable_irq()
456 __func__, mask, bit, irq); sable_lynx_enable_irq()
463 unsigned long bit, mask; sable_lynx_disable_irq() local
465 bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq]; sable_lynx_disable_irq()
467 mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit; sable_lynx_disable_irq()
468 sable_lynx_irq_swizzle->update_irq_hw(bit, mask); sable_lynx_disable_irq()
471 printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n", sable_lynx_disable_irq()
472 __func__, mask, bit, irq); sable_lynx_disable_irq()
479 unsigned long bit, mask; sable_lynx_mask_and_ack_irq() local
481 bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq]; sable_lynx_mask_and_ack_irq()
483 mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit; sable_lynx_mask_and_ack_irq()
484 sable_lynx_irq_swizzle->update_irq_hw(bit, mask); sable_lynx_mask_and_ack_irq()
485 sable_lynx_irq_swizzle->ack_irq_hw(bit); sable_lynx_mask_and_ack_irq()
503 int bit, irq; sable_lynx_srm_device_interrupt() local
505 bit = (vector - 0x800) >> 4; sable_lynx_srm_device_interrupt()
506 irq = sable_lynx_irq_swizzle->mask_to_irq[bit]; sable_lynx_srm_device_interrupt()
508 printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n", sable_lynx_srm_device_interrupt()
509 __func__, vector, bit, irq); sable_lynx_srm_device_interrupt()
/linux-4.1.27/drivers/usb/musb/
H A Dmusb_regs.h229 #define MUSB_FADDR 0x00 /* 8-bit */
230 #define MUSB_POWER 0x01 /* 8-bit */
232 #define MUSB_INTRTX 0x02 /* 16-bit */
236 #define MUSB_INTRUSB 0x0A /* 8 bit */
237 #define MUSB_INTRUSBE 0x0B /* 8 bit */
239 #define MUSB_INDEX 0x0E /* 8 bit */
240 #define MUSB_TESTMODE 0x0F /* 8 bit */
246 #define MUSB_DEVCTL 0x60 /* 8 bit */
247 #define MUSB_BABBLE_CTL 0x61 /* 8 bit */
250 #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
251 #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
252 #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
253 #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
256 #define MUSB_HWVERS 0x6C /* 8 bit */
257 #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
258 #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
259 #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
260 #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
261 #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
262 #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
263 #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
265 #define MUSB_EPINFO 0x78 /* 8 bit */
266 #define MUSB_RAMINFO 0x79 /* 8 bit */
267 #define MUSB_LINKINFO 0x7a /* 8 bit */
268 #define MUSB_VPLEN 0x7b /* 8 bit */
269 #define MUSB_HS_EOF1 0x7c /* 8 bit */
270 #define MUSB_FS_EOF1 0x7d /* 8 bit */
271 #define MUSB_LS_EOF1 0x7e /* 8 bit */
449 #define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
450 #define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
451 #define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
455 #define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
456 #define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
458 #define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
459 #define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
465 #define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
467 #define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
468 #define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
469 #define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
470 #define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
471 #define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
/linux-4.1.27/drivers/block/drbd/
H A Ddrbd_vli.h29 * At a granularity of 4KiB storage represented per bit,
36 * by encoding runlengths of bit polarity.
39 * But then we have to store the value of the first bit.
40 * The first bit of information thus shall encode if the first runlength
45 * even when encoding the runlength as fixed size 32bit/64bit integers.
68 * * various bit based with different code word length.
81 * __little endian__ bitstream, least significant bit first (left most)
85 * 10 levels can be described in 8bit, with minimal overhead
89 * last level (+1 data bit, so it makes 64bit total). The only worse code when
90 * encoding bit polarity runlength is 1 plain bits => 2 code bits.
194 /* code from here down is independend of actually used bit code */
198 * This encodes arbitrary bit length, not whole bytes: we have a bit-stream,
206 /* the current bit within *b, nomalized: 0..7 */
207 unsigned int bit; member in struct:bitstream_cursor
210 /* initialize cursor to point to first bit of stream */ bitstream_cursor_reset()
214 cur->bit = 0; bitstream_cursor_reset()
221 bits += cur->bit; bitstream_cursor_advance()
223 cur->bit = bits & 7; bitstream_cursor_advance()
268 if ((bs->cur.b + ((bs->cur.bit + bits -1) >> 3)) - bs->buf >= bs->buf_len) bitstream_put_bits()
275 *b++ |= (val & 0xff) << bs->cur.bit; bitstream_put_bits()
277 for (tmp = 8 - bs->cur.bit; tmp < bits; tmp += 8) bitstream_put_bits()
301 if (bs->cur.b + ((bs->cur.bit + bs->pad_bits + bits -1) >> 3) - bs->buf >= bs->buf_len) bitstream_get_bits()
303 - bs->cur.bit - bs->pad_bits; bitstream_get_bits()
312 n = (bs->cur.bit + bits + 7) >> 3; bitstream_get_bits()
313 /* n may be at most 9, if cur.bit + bits > 64 */ bitstream_get_bits()
317 val = le64_to_cpu(val) << (8 - bs->cur.bit); bitstream_get_bits()
321 val |= bs->cur.b[0] >> bs->cur.bit; bitstream_get_bits()
/linux-4.1.27/drivers/acpi/acpica/
H A Dtbutils.c215 * DESCRIPTION: Get one root table entry. Handles 32-bit and 64-bit cases on
216 * both 32-bit and 64-bit platforms
218 * NOTE: acpi_physical_address is 32-bit on 32-bit platforms, 64-bit on
219 * 64-bit platforms.
229 * Get the table physical address (32-bit for RSDT, 64-bit for XSDT): acpi_tb_get_root_table_entry()
230 * Note: Addresses are 32-bit aligned (not 64) in both RSDT and XSDT acpi_tb_get_root_table_entry()
234 * 32-bit platform, RSDT: Return 32-bit table entry acpi_tb_get_root_table_entry()
235 * 64-bit platform, RSDT: Expand 32-bit to 64-bit and return acpi_tb_get_root_table_entry()
241 * 32-bit platform, XSDT: Truncate 64-bit to 32-bit and return acpi_tb_get_root_table_entry()
242 * 64-bit platform, XSDT: Move (unaligned) 64-bit to local, acpi_tb_get_root_table_entry()
243 * return 64-bit acpi_tb_get_root_table_entry()
250 /* Will truncate 64-bit address to 32 bits, issue warning */ acpi_tb_get_root_table_entry()
253 "64-bit Physical Address in XSDT is too large (0x%8.8X%8.8X)," acpi_tb_get_root_table_entry()
310 * RSDP contains an XSDT (64-bit physical addresses). We must use acpi_tb_parse_root_table()
317 /* Root table is an RSDT (32-bit physical addresses) */ acpi_tb_parse_root_table()
373 * and 32bit/64bit FACS, which are not actually present in the acpi_tb_parse_root_table()
382 /* Get the table physical address (32-bit for RSDT, 64-bit for XSDT) */ acpi_tb_parse_root_table()
H A Dtbfadt.c212 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " acpi_tb_init_generic_address()
222 * The 64-bit Address field is non-aligned in the byte packed acpi_tb_init_generic_address()
240 * address32 - 32-bit address of the register
241 * address64 - 64-bit address of the register
243 * RETURN: The resolved 64-bit address
245 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
251 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
256 * By default, as per the ACPICA specification, a valid 64-bit address is
257 * used regardless of the value of the 32-bit address. However, this
268 /* 64-bit address is zero, use 32-bit address */ acpi_tb_select_address()
275 /* Address mismatch between 32-bit and 64-bit versions */ acpi_tb_select_address()
279 "0x%8.8X/0x%8.8X%8.8X, using %u-bit address", acpi_tb_select_address()
285 /* 32-bit address override */ acpi_tb_select_address()
292 /* Default is to use the 64-bit address */ acpi_tb_select_address()
433 * Expand 32-bit addresses to 64-bit as necessary. Also validate
439 * Notes on 64-bit register addresses:
441 * After this FADT conversion, later ACPICA code will only use the 64-bit "X"
444 * The 64-bit X fields are optional extensions to the original 32-bit FADT
447 * 32-bit V1.0 fields to the 64-bit X fields if the the 64-bit X field is
450 * For ACPI 1.0 FADTs (that contain no 64-bit addresses), all 32-bit address
451 * fields are expanded to the corresponding 64-bit X fields in the internal
454 * For ACPI 2.0+ FADTs, all valid (non-zero) 32-bit address fields are expanded
455 * to the corresponding 64-bit X fields, if the 64-bit field is originally
456 * zero. Adhering to the ACPI specification, we completely ignore the 32-bit
457 * field if the 64-bit field is valid, regardless of whether the host OS is
458 * 32-bit or 64-bit.
503 * Expand the 32-bit DSDT addresses to 64-bit as necessary. acpi_tb_convert_fadt()
504 * Later ACPICA code will always use the X 64-bit field. acpi_tb_convert_fadt()
516 /* Examine all of the 64-bit extended address fields (X fields) */ acpi_tb_convert_fadt()
520 * Get the 32-bit and 64-bit addresses, as well as the register acpi_tb_convert_fadt()
539 * Expand the ACPI 1.0 32-bit addresses to the ACPI 2.0 64-bit "X" acpi_tb_convert_fadt()
541 * the 64-bit address structures. acpi_tb_convert_fadt()
544 * Now always use the 64-bit address if it is valid (non-zero), in acpi_tb_convert_fadt()
545 * accordance with the ACPI specification which states that a 64-bit acpi_tb_convert_fadt()
546 * address supersedes the 32-bit version. This behavior can be acpi_tb_convert_fadt()
549 * During 64-bit address construction and verification, acpi_tb_convert_fadt()
561 * Note: space_id is always I/O for 32-bit legacy address fields acpi_tb_convert_fadt()
566 /* 64-bit address is zero, use 32-bit address */ acpi_tb_convert_fadt()
583 "0x%8.8X/0x%8.8X%8.8X, using %u-bit address", acpi_tb_convert_fadt()
592 /* 32-bit address override */ acpi_tb_convert_fadt()
612 * legacy length field and the corresponding 64-bit X length field. acpi_tb_convert_fadt()
614 * check. (GPE registers can be larger than the 64-bit GAS structure acpi_tb_convert_fadt()
/linux-4.1.27/drivers/net/wireless/ti/wl12xx/
H A Dreg.h39 Host Software Reset - 32bit RW
42 0 SOFT_RESET Soft Reset - When this bit is set,
48 contents of the EEPROM. When this bit is cleared
62 Host Interrupt Mask Register - 32bit (RW)
64 Setting a bit in this register masks the
92 Host Interrupt Mask Set 16bit, (Write only)
94 Setting a bit in this register sets
102 Host Interrupt Mask Clear 16bit,(Write only)
104 Setting a bit in this register clears
113 16bit,(Read only)
124 16bit,(Read only)
135 16bit,(Write only)
153 Halt eCPU - 32bit RW
155 0 HALT_ECPU Halt Embedded CPU - This bit is the
156 compliment of bit 1 (MDATA2) in the SOR_CFG register.
157 During a hardware reset, this bit holds
160 set this bit (pull down MDATA2).
161 The host clears this bit after downloading the firmware into
163 When loading firmware from Flash, clear this bit (pull up MDATA2)
175 EEPROM Burst Read Start - 32bit RW
179 Setting this bit starts a burst read from
181 If this bit is set (after reset) before an EEPROM read/write,
185 TheWlan hardware hardware clears this bit automatically.
257 Command Mailbox Pointer - 32bit RW
272 Information Mailbox Pointer - 32bit RW
287 EEPROM Read/Write Request 32bit RW
289 1 EE_READ - EEPROM Read Request 1 - Setting this bit
293 The Wlan hardware hardware clears this bit automatically.
294 EE_DATA is valid when this bit is cleared.
296 0 EE_WRITE - EEPROM Write Request - Setting this bit
299 The Wlan hardware hardware clears this bit automatically.
306 EEPROM Address - 32bit RW
314 EEPROM Data - 32bit RW
323 EEPROM Base Address - 32bit RW
326 [23:15] of the 24-bit Wlan hardware memory
334 GPIO Output Values -32bit, RW
344 Contention window -32bit, RW
400 Rate & Modulation info into a single 16-bit field.
494 * Host Command Interrupt. Setting this bit masks
503 * sets this bit to acknowledge that it received
/linux-4.1.27/arch/mips/loongson/common/
H A Ddma-swiotlb.c110 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from phys_to_dma()
111 * Loongson-3's 48bit address space and embed it into 40bit */ phys_to_dma()
122 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from dma_to_phys()
123 * Loongson-3's 48bit address space and embed it into 40bit */ dma_to_phys()
H A Dmem.c31 int bit; prom_init_memory() local
33 bit = fls(memsize + highmemsize); prom_init_memory()
34 if (bit != ffs(memsize + highmemsize)) prom_init_memory()
35 bit += 20; prom_init_memory()
37 bit = bit + 20 - 1; prom_init_memory()
41 0x80000000ul, (1 << bit)); prom_init_memory()
/linux-4.1.27/drivers/input/mouse/
H A Dcyapa.h61 * bit 7: Valid interrupt source
62 * bit 6 - 4: Reserved
63 * bit 3 - 2: Power status
64 * bit 1 - 0: Device status
75 * bit 7 - 4: Number of touched finger
76 * bit 3: Valid data
77 * bit 2: Middle Physical Button
78 * bit 1: Right Physical Button
79 * bit 0: Left physical Button
100 * bit 7: Busy
101 * bit 6 - 5: Reserved
102 * bit 4: Bootloader running
103 * bit 3 - 2: Reserved
104 * bit 1: Watchdog Reset
105 * bit 0: Checksum valid
120 * bit 7: Invalid
121 * bit 6: Invalid security key
122 * bit 5: Bootloading
123 * bit 4: Command checksum
124 * bit 3: Flash protection error
125 * bit 2: Flash checksum error
126 * bit 1 - 0: Reserved
/linux-4.1.27/drivers/pcmcia/
H A Dtopic.h36 #define TOPIC_SOCKET_CONTROL 0x0090 /* 32 bit */
39 #define TOPIC_SLOT_CONTROL 0x00a0 /* 8 bit */
48 #define TOPIC_CARD_CONTROL 0x00a1 /* 8 bit */
56 #define TOPIC97_INT_CONTROL 0x00a1 /* 8 bit */
63 #define TOPIC_CARD_DETECT 0x00a3 /* 8 bit */
69 #define TOPIC_REGISTER_CONTROL 0x00a4 /* 32 bit */
83 #define TOPIC97_MISC1 0x00ad /* 8bit */
90 #define TOPIC97_MISC2 0x00ae /* 8 bit */
97 #define TOPIC97_ZOOM_VIDEO_CONTROL 0x009c /* 8 bit */
100 #define TOPIC97_AUDIO_VIDEO_SWITCH 0x003c /* 8 bit */
104 #define TOPIC_EXCA_IF_CONTROL 0x3e /* 8 bit */
107 #define TOPIC_PCI_CFG_PPBCN 0x3e /* 16-bit */
146 /* enable 3.3V support for 16bit cards */ topic95_override()
150 /* tell yenta to use exca registers to power 16bit cards */ topic95_override()
/linux-4.1.27/drivers/staging/speakup/
H A Dspeakup_dtlk.h6 #define TTS_READABLE 0x80 /* mask for bit which is nonzero if a
8 #define TTS_SPEAKING 0x40 /* mask for SYNC bit, which is nonzero
13 #define TTS_SPEAKING2 0x20 /* mask for SYNC2 bit,
16 #define TTS_WRITABLE 0x10 /* mask for RDY bit, which when set to
19 bit goes zero 2-3 usec after
22 #define TTS_ALMOST_FULL 0x08 /* mask for AF bit: When set to 1,
27 #define TTS_ALMOST_EMPTY 0x04 /* mask for AE bit: When set to 1,
/linux-4.1.27/arch/mips/include/asm/sgi/
H A Dgio.h41 * 32-bit IDs are divided into
43 * bit 7 0=GIO Product ID is 8 bits wide
46 * bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
47 * bit 17 0=no ROM present
54 * 8-bit IDs
60 * 0x07 16 bit SCSI Card [*]
71 * [*] Device provide 32-bit ID.
/linux-4.1.27/arch/arm/mach-ep93xx/
H A Dmicro9.c29 * Micro9-High has up to 64MB of 32-bit flash on CS1
30 * Micro9-Mid has up to 64MB of either 32-bit or 16-bit flash on CS1
32 * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
41 return 4; /* 32-bit */ micro9_detect_bootwidth()
43 return 2; /* 16-bit */ micro9_detect_bootwidth()
/linux-4.1.27/net/netfilter/
H A Dnf_conntrack_labels.c23 bool nf_connlabel_match(const struct nf_conn *ct, u16 bit) nf_connlabel_match() argument
30 return bit < label_bits(labels) && test_bit(bit, labels->bits); nf_connlabel_match()
34 int nf_connlabel_set(struct nf_conn *ct, u16 bit) nf_connlabel_set() argument
38 if (!labels || bit >= label_bits(labels)) nf_connlabel_set()
41 if (test_bit(bit, labels->bits)) nf_connlabel_set()
44 if (!test_and_set_bit(bit, labels->bits)) nf_connlabel_set()
/linux-4.1.27/sound/soc/nuc900/
H A Dnuc900-audio.h38 /* bit definition of REG_ACTL_CON register */
48 /* bit definition of REG_ACTL_RESET register */
68 /* bit definition of REG_ACTL_ACCON register */
75 /* bit definition of ACTL_RSR register */
80 /* bit definition of ACTL_PSR register */
85 /* bit definition of ACTL_ACOS0 register */
92 /* bit definition of ACTL_ACOS1 register */
/linux-4.1.27/sound/soc/omap/
H A Domap-mcpdm.h45 * MCPDM_IRQ bit fields
63 * MCPDM_DMAENABLE bit fields
70 * MCPDM_CTRL bit fields
73 #define MCPDM_PDM_UPLINK_EN(x) (1 << (x - 1)) /* ch1 is at bit 0 */
74 #define MCPDM_PDM_DOWNLINK_EN(x) (1 << (x + 2)) /* ch1 is at bit 3 */
89 * MCPDM_FIFO_CTRL bit fields
96 * MCPDM_DN_OFFSET bit fields
/linux-4.1.27/drivers/char/
H A Dpc8736x_gpio.c49 #define PC8736X_GPIO_CT 32 /* minors matching 4 8 bit ports */
154 int port, bit, val; pc8736x_gpio_get() local
157 bit = minor & 7; pc8736x_gpio_get()
159 val >>= bit; pc8736x_gpio_get() local
162 dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n", pc8736x_gpio_get()
163 minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit, pc8736x_gpio_get()
171 int port, bit, curval; pc8736x_gpio_set() local
175 bit = minor & 7; pc8736x_gpio_set()
178 dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n", pc8736x_gpio_set()
180 curval, bit, (curval & ~(1 << bit)), val, (val << bit)); pc8736x_gpio_set()
182 val = (curval & ~(1 << bit)) | (val << bit); pc8736x_gpio_set()
184 dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)" pc8736x_gpio_set()
185 " %2x -> %2x\n", minor, port, bit, curval, val); pc8736x_gpio_set()
198 int port, bit; pc8736x_gpio_current() local
201 bit = minor & 7; pc8736x_gpio_current()
202 return ((pc8736x_gpio_shadow[port] >> bit) & 0x01); pc8736x_gpio_current()
/linux-4.1.27/arch/mips/cavium-octeon/
H A Docteon-irq.c41 u8 bit; member in struct:octeon_ciu_chip_data::__anon1863::__anon1865
52 u8 bit; member in struct:octeon_core_chip_data
59 static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line, octeon_irq_set_ciu_mapping() argument
72 cd->bit = bit; octeon_irq_set_ciu_mapping()
76 octeon_irq_ciu_to_irq[line][bit] = irq; octeon_irq_set_ciu_mapping()
90 int irq, int line, int bit) octeon_irq_force_ciu_mapping()
92 return irq_domain_associate(domain, irq, line << 6 | bit); octeon_irq_force_ciu_mapping()
116 unsigned int bit = cd->bit; octeon_irq_core_ack() local
123 clear_c0_status(0x100 << bit); octeon_irq_core_ack()
125 if (bit < 2) octeon_irq_core_ack()
126 clear_c0_cause(0x100 << bit); octeon_irq_core_ack()
138 set_c0_status(0x100 << cd->bit); octeon_irq_core_eoi()
145 unsigned int mask = 0x100 << cd->bit; octeon_irq_core_set_enable_local()
213 cd->bit = i; octeon_irq_init_core()
268 __set_bit(cd->bit, pen); octeon_irq_ciu_enable()
277 __set_bit(cd->bit, pen); octeon_irq_ciu_enable()
300 __set_bit(cd->bit, pen); octeon_irq_ciu_enable_local()
309 __set_bit(cd->bit, pen); octeon_irq_ciu_enable_local()
332 __clear_bit(cd->bit, pen); octeon_irq_ciu_disable_local()
341 __clear_bit(cd->bit, pen); octeon_irq_ciu_disable_local()
371 __clear_bit(cd->bit, pen); for_each_online_cpu()
404 __set_bit(cd->bit, pen); for_each_online_cpu()
429 mask = 1ull << (cd->bit); octeon_irq_ciu_enable_v2()
437 set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); octeon_irq_ciu_enable_v2()
441 set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); octeon_irq_ciu_enable_v2()
457 mask = 1ull << (cd->bit); octeon_irq_ciu_enable_sum2()
473 mask = 1ull << (cd->bit); octeon_irq_ciu_disable_local_sum2()
486 mask = 1ull << (cd->bit); octeon_irq_ciu_ack_sum2()
498 mask = 1ull << (cd->bit); octeon_irq_ciu_disable_all_sum2()
517 mask = 1ull << (cd->bit); octeon_irq_ciu_enable_local_v2()
521 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror)); octeon_irq_ciu_enable_local_v2()
525 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror)); octeon_irq_ciu_enable_local_v2()
536 mask = 1ull << (cd->bit); octeon_irq_ciu_disable_local_v2()
540 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror)); octeon_irq_ciu_disable_local_v2()
544 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror)); octeon_irq_ciu_disable_local_v2()
550 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
558 mask = 1ull << (cd->bit); octeon_irq_ciu_ack()
579 mask = 1ull << (cd->bit); octeon_irq_ciu_disable_all_v2()
584 clear_bit(cd->bit, for_each_online_cpu()
591 clear_bit(cd->bit, for_each_online_cpu()
609 mask = 1ull << (cd->bit); octeon_irq_ciu_enable_all_v2()
614 set_bit(cd->bit, for_each_online_cpu()
621 set_bit(cd->bit, for_each_online_cpu()
769 __set_bit(cd->bit, pen); for_each_online_cpu()
771 __clear_bit(cd->bit, pen); for_each_online_cpu()
806 mask = 1ull << cd->bit; octeon_irq_ciu_set_affinity_v2()
814 set_bit(cd->bit, pen); for_each_online_cpu()
817 clear_bit(cd->bit, pen); for_each_online_cpu()
827 set_bit(cd->bit, pen); for_each_online_cpu()
830 clear_bit(cd->bit, pen); for_each_online_cpu()
851 mask = 1ull << cd->bit; octeon_irq_ciu_set_affinity_sum2()
1057 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit) octeon_irq_ciu_is_edge() argument
1062 switch (bit) { octeon_irq_ciu_is_edge()
1073 switch (bit) { octeon_irq_ciu_is_edge()
1143 unsigned int ciu, bit; octeon_irq_ciu_xlat() local
1147 bit = intspec[1]; octeon_irq_ciu_xlat()
1149 if (ciu >= dd->num_sum || bit > 63) octeon_irq_ciu_xlat()
1152 *out_hwirq = (ciu << 6) | bit; octeon_irq_ciu_xlat()
1177 unsigned int bit = hw & 63; octeon_irq_ciu_map() local
1184 if (line == 0 && bit >= 16 && bit <32) octeon_irq_ciu_map()
1187 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0) octeon_irq_ciu_map()
1191 if (octeon_irq_ciu_is_edge(line, bit)) octeon_irq_ciu_map()
1192 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu_map()
1196 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu_map()
1200 if (octeon_irq_ciu_is_edge(line, bit)) octeon_irq_ciu_map()
1201 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu_map()
1205 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu_map()
1216 unsigned int line, bit; octeon_irq_gpio_map() local
1223 bit = (hw + gpiod->base_hwirq) & 63; octeon_irq_gpio_map()
1225 octeon_irq_ciu_to_irq[line][bit] != 0) octeon_irq_gpio_map()
1228 r = octeon_irq_set_ciu_mapping(virq, line, bit, hw, octeon_irq_gpio_map()
1252 int bit = fls64(ciu_sum) - 1; octeon_irq_ip2_ciu() local
1253 int irq = octeon_irq_ciu_to_irq[0][bit]; octeon_irq_ip2_ciu()
1269 int bit = fls64(ciu_sum) - 1; octeon_irq_ip3_ciu() local
1270 int irq = octeon_irq_ciu_to_irq[1][bit]; octeon_irq_ip3_ciu()
1288 int bit = fls64(ciu_sum) - 1; octeon_irq_ip4_ciu() local
1289 int irq = octeon_irq_ciu_to_irq[2][bit]; octeon_irq_ip4_ciu()
1600 mask = 1ull << (cd->bit); octeon_irq_ciu2_wd_enable()
1617 mask = 1ull << (cd->bit); octeon_irq_ciu2_enable()
1632 mask = 1ull << (cd->bit); octeon_irq_ciu2_enable_local()
1648 mask = 1ull << (cd->bit); octeon_irq_ciu2_disable_local()
1664 mask = 1ull << (cd->bit); octeon_irq_ciu2_ack()
1678 mask = 1ull << (cd->bit); octeon_irq_ciu2_disable_all()
1750 mask = 1ull << cd->bit; octeon_irq_ciu2_set_affinity()
1855 unsigned int ciu, bit; octeon_irq_ciu2_xlat() local
1858 bit = intspec[1]; octeon_irq_ciu2_xlat()
1860 *out_hwirq = (ciu << 6) | bit; octeon_irq_ciu2_xlat()
1866 static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit) octeon_irq_ciu2_is_edge() argument
1871 switch (bit) { octeon_irq_ciu2_is_edge()
1881 switch (bit) { octeon_irq_ciu2_is_edge()
1896 unsigned int bit = hw & 63; octeon_irq_ciu2_map() local
1908 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0) octeon_irq_ciu2_map()
1911 if (octeon_irq_ciu2_is_edge(line, bit)) octeon_irq_ciu2_map()
1912 octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu2_map()
1916 octeon_irq_set_ciu_mapping(virq, line, bit, 0, octeon_irq_ciu2_map()
1932 int bit; octeon_irq_ciu2() local
1949 bit = fls64(src) - 1; octeon_irq_ciu2()
1950 irq = octeon_irq_ciu_to_irq[line][bit]; octeon_irq_ciu2()
2079 int bit; member in struct:octeon_irq_cib_chip_data
2091 en |= 1ull << cd->bit; octeon_irq_cib_enable()
2105 en &= ~(1ull << cd->bit); octeon_irq_cib_disable()
2168 cd->bit = hw; octeon_irq_cib_map()
2205 pr_err("ERROR: CIB bit %d@%llx IRQ unhandled, disabling\n", octeon_irq_cib_handler()
2216 /* If edge, acknowledge the bit we will be sending. */ octeon_irq_cib_handler()
89 octeon_irq_force_ciu_mapping(struct irq_domain *domain, int irq, int line, int bit) octeon_irq_force_ciu_mapping() argument
/linux-4.1.27/arch/x86/um/asm/
H A Dchecksum.h9 * and adds in "sum" (32-bit)
11 * returns a 32-bit number suitable for feeding into itself
17 * it's best to have buff aligned on a 32-bit boundary
41 * here even more important to align src and dst on a 32-bit (or even
42 * better 64-bit) boundary
58 * csum_fold - Fold and invert a 32bit checksum.
59 * sum: 32bit unfolded sum
61 * Fold a 32bit running checksum to 16bit and invert it. This is usually
63 * Make sure not to mix with 64bit checksums.
83 * @sum: initial sum to be added in (32bit unfolded)
86 * 32bit unfolded.
103 * returns a 16-bit checksum, already complemented
/linux-4.1.27/arch/sh/boards/mach-dreamcast/
H A Dirq.c25 * triggered, its corresponding bit in the Event Status Registers (ESRs)
26 * is set, and that bit should be rewritten to the ESR to acknowledge that
29 * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event
55 /* Return the hardware event's bit position within the EMR/ESR */
60 * (logically mapped to the corresponding bit for the hardware event).
63 /* Disable the hardware event by masking its bit in its EMR */ disable_systemasic_irq()
75 /* Enable the hardware event by setting its bit in its EMR */ enable_systemasic_irq()
87 /* Acknowledge a hardware event by writing its bit back to its ESR */ mask_ack_systemasic_irq()
109 __u32 j, bit; systemasic_irq_demux() local
131 /* Now scan and find the first set bit as the event to map */ systemasic_irq_demux()
132 for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { systemasic_irq_demux()
133 if (status & bit) { systemasic_irq_demux()
/linux-4.1.27/arch/alpha/lib/
H A Ddivide.S13 * __divqu: 64-bit unsigned long divide
14 * __remqu: 64-bit unsigned long remainder
15 * __divqs/__remqs: signed 64-bit
16 * __divlu/__remlu: unsigned 32-bit
17 * __divls/__remls: signed 32-bit
26 * This is a rather simple bit-at-a-time algorithm: it's very good
27 * at dividing random 64-bit numbers, but the more usual case where
36 * $0 - current bit
78 * For 32-bit operations, we need to extend to 64-bit
116 * shift divisor left, using 3-bit shifts for
117 * 32-bit divides as we can't overflow. Three-bit
/linux-4.1.27/drivers/clocksource/
H A Dtimer-u300.c35 /* Reset OS Timer 32bit (-/W) */
38 /* Enable OS Timer 32bit (-/W) */
41 /* Disable OS Timer 32bit (-/W) */
44 /* OS Timer Mode Register 32bit (-/W) */
48 /* OS Timer Status Register 32bit (R/-) */
59 /* OS Timer Current Count Register 32bit (R/-) */
61 /* OS Timer Terminal Count Register 32bit (R/W) */
63 /* OS Timer Interrupt Enable Register 32bit (-/W) */
67 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
71 /* Reset DD Timer 32bit (-/W) */
74 /* Enable DD Timer 32bit (-/W) */
77 /* Disable DD Timer 32bit (-/W) */
80 /* DD Timer Mode Register 32bit (-/W) */
84 /* DD Timer Status Register 32bit (R/-) */
95 /* DD Timer Current Count Register 32bit (R/-) */
97 /* DD Timer Terminal Count Register 32bit (R/W) */
99 /* DD Timer Interrupt Enable Register 32bit (-/W) */
103 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
107 /* Reset GP1 Timer 32bit (-/W) */
110 /* Enable GP1 Timer 32bit (-/W) */
113 /* Disable GP1 Timer 32bit (-/W) */
116 /* GP1 Timer Mode Register 32bit (-/W) */
120 /* GP1 Timer Status Register 32bit (R/-) */
131 /* GP1 Timer Current Count Register 32bit (R/-) */
133 /* GP1 Timer Terminal Count Register 32bit (R/W) */
135 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
139 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
143 /* Reset GP2 Timer 32bit (-/W) */
146 /* Enable GP2 Timer 32bit (-/W) */
149 /* Disable GP2 Timer 32bit (-/W) */
152 /* GP2 Timer Mode Register 32bit (-/W) */
156 /* GP2 Timer Status Register 32bit (R/-) */
167 /* GP2 Timer Current Count Register 32bit (R/-) */
169 /* GP2 Timer Terminal Count Register 32bit (R/W) */
171 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
175 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
/linux-4.1.27/arch/mips/loongson1/common/
H A Dirq.c29 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; ls1x_irq_ack() local
33 | (1 << bit), LS1X_INTC_INTCLR(n)); ls1x_irq_ack()
38 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; ls1x_irq_mask() local
42 & ~(1 << bit), LS1X_INTC_INTIEN(n)); ls1x_irq_mask()
47 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; ls1x_irq_mask_ack() local
51 & ~(1 << bit), LS1X_INTC_INTIEN(n)); ls1x_irq_mask_ack()
53 | (1 << bit), LS1X_INTC_INTCLR(n)); ls1x_irq_mask_ack()
58 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f; ls1x_irq_unmask() local
62 | (1 << bit), LS1X_INTC_INTIEN(n)); ls1x_irq_unmask()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dvr1000.h62 * whether the access is for 8 or 16bit IO... this ensures that
67 * 0x00000000 to 0x04000000 8bit, slow
68 * 0x04000000 to 0x08000000 16bit, slow
69 * 0x08000000 to 0x0C000000 16bit, net
70 * 0x0C000000 to 0x10000000 16bit, fast
82 * nGCS2 - 8bit, slow
83 * nGCS3 - 16bit, slow
84 * nGCS4 - 16bit, net
85 * nGCS5 - 16bit, fast
/linux-4.1.27/arch/arm/nwfpe/
H A Dfpsr.h26 The FPSR is a 32 bit register consisting of 4 parts, each exactly
34 The FPCR is a 32 bit register consisting of bit flags.
70 #define BIT_NE 0x00000200 /* NaN exception bit */
71 #define BIT_ND 0x00000100 /* no denormalized numbers bit */
88 #define BIT_RU 0x80000000 /* rounded up bit */
89 #define BIT_IE 0x10000000 /* inexact bit */
90 #define BIT_MO 0x08000000 /* mantissa overflow bit */
91 #define BIT_EO 0x04000000 /* exponent overflow bit */
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/phy/
H A Dphy_qmath.c20 * Description: This function make 16 bit unsigned multiplication.
21 * To fit the output into 16 bits the 32 bit multiplication result is right
30 * Description: This function make 16 bit multiplication and return the result
33 * is done to remove the extra sign bit formed due to the multiplication.
34 * When both the 16bit inputs are 0x8000 then the output is saturated to
49 * Description: This function add two 32 bit numbers and return the 32bit
66 * Description: This function add two 16 bit numbers and return the 16bit
85 * Description: This function make 16 bit subtraction and return the 16bit
104 * Description: This function make a 32 bit saturated left shift when the
105 * specified shift is +ve. This function will make a 32 bit right shift when
129 * Description: This function make a 16 bit saturated left shift when the
130 * specified shift is +ve. This function will make a 16 bit right shift when
154 * Description: This function make a 16 bit right shift when shift is +ve.
155 * This function make a 16 bit saturated left shift when shift is -ve. This
165 * 32 bit number. Example: qm_norm32(0x00000080) = 23
255 * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e. qm_log10()
256 * at the right side of 30th bit. qm_log10()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Ddrxk.h19 * @antenna_gpio: GPIO bit used to control the antenna
20 * @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
33 * On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is

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