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Searched refs:armada_reg_queue_set (Results 1 – 3 of 3) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/armada/
Darmada_overlay.c190 armada_reg_queue_set(dplane->vbl.regs, idx, sy, in armada_plane_update()
192 armada_reg_queue_set(dplane->vbl.regs, idx, su, in armada_plane_update()
194 armada_reg_queue_set(dplane->vbl.regs, idx, sv, in armada_plane_update()
196 armada_reg_queue_set(dplane->vbl.regs, idx, sy, in armada_plane_update()
198 armada_reg_queue_set(dplane->vbl.regs, idx, su, in armada_plane_update()
200 armada_reg_queue_set(dplane->vbl.regs, idx, sv, in armada_plane_update()
204 armada_reg_queue_set(dplane->vbl.regs, idx, val, in armada_plane_update()
207 armada_reg_queue_set(dplane->vbl.regs, idx, val, in armada_plane_update()
214 armada_reg_queue_set(dplane->vbl.regs, idx, val, in armada_plane_update()
220 armada_reg_queue_set(dplane->vbl.regs, idx, val, in armada_plane_update()
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Darmada_crtc.c169 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); in armada_drm_crtc_calc_fb()
170 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); in armada_drm_crtc_calc_fb()
547 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); in armada_drm_crtc_mode_set()
581 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); in armada_drm_crtc_mode_set()
582 armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN); in armada_drm_crtc_mode_set()
583 armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN); in armada_drm_crtc_mode_set()
584 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); in armada_drm_crtc_mode_set()
585 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); in armada_drm_crtc_mode_set()
586 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, in armada_drm_crtc_mode_set()
615 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL); in armada_drm_crtc_mode_set()
Darmada_crtc.h28 #define armada_reg_queue_set(_r, _i, _v, _o) \ macro