Searched refs:arm_lpae_s1_cfg (Results 1 – 4 of 4) sorted by relevance
645 cfg->arm_lpae_s1_cfg.tcr = reg; in arm_64_lpae_alloc_pgtable_s1()655 cfg->arm_lpae_s1_cfg.mair[0] = reg; in arm_64_lpae_alloc_pgtable_s1()656 cfg->arm_lpae_s1_cfg.mair[1] = 0; in arm_64_lpae_alloc_pgtable_s1()666 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()667 cfg->arm_lpae_s1_cfg.ttbr[1] = 0; in arm_64_lpae_alloc_pgtable_s1()773 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE; in arm_32_lpae_alloc_pgtable_s1()774 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff; in arm_32_lpae_alloc_pgtable_s1()
59 } arm_lpae_s1_cfg; member
765 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_init_context_bank()767 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32; in arm_smmu_init_context_bank()771 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; in arm_smmu_init_context_bank()773 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32; in arm_smmu_init_context_bank()785 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; in arm_smmu_init_context_bank()788 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; in arm_smmu_init_context_bank()799 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; in arm_smmu_init_context_bank()801 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; in arm_smmu_init_context_bank()
343 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; in ipmmu_domain_init_context()357 ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]); in ipmmu_domain_init_context()