Searched refs:_ULCAST_ (Results 1 – 7 of 7) sorted by relevance
36 #define _ULCAST_ macro38 #define _ULCAST_ (unsigned long) macro200 #define PG_RIE (_ULCAST_(1) << 31)201 #define PG_XIE (_ULCAST_(1) << 30)202 #define PG_ELPA (_ULCAST_(1) << 29)203 #define PG_ESP (_ULCAST_(1) << 28)204 #define PG_IEC (_ULCAST_(1) << 27)209 #define IE_SW0 (_ULCAST_(1) << 8)210 #define IE_SW1 (_ULCAST_(1) << 9)211 #define IE_IRQ0 (_ULCAST_(1) << 10)[all …]
167 #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8)169 #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0)173 #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15)175 #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0)183 #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0)187 #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8)189 #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)193 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)195 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0)199 #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0)[all …]
174 #define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB)176 #define MSA_IR_PROCF (_ULCAST_(0xff) << MSA_IR_PROCB)178 #define MSA_IR_WRPF (_ULCAST_(0x1) << MSA_IR_WRPB)182 #define MSA_CSR_RMF (_ULCAST_(0x3) << MSA_CSR_RMB)188 #define MSA_CSR_FLAGSF (_ULCAST_(0x1f) << MSA_CSR_FLAGSB)190 #define MSA_CSR_FLAGS_IF (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)192 #define MSA_CSR_FLAGS_UF (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)194 #define MSA_CSR_FLAGS_OF (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)196 #define MSA_CSR_FLAGS_ZF (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)198 #define MSA_CSR_FLAGS_VF (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)[all …]
122 #define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0)123 #define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0)124 #define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0)125 #define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0)126 #define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0)130 #define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23)132 #define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19)133 #define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19)134 #define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19)135 #define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19)[all …]
74 #define MVPCONTROL_EVP (_ULCAST_(1))77 #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)80 #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)85 #define MVPCONF0_PTC ( _ULCAST_(0xff))87 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)89 #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)91 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)93 #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)95 #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)100 #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)[all …]
100 #define CAUSEF_DC (_ULCAST_(1) << 27)
34 #define C_TI (_ULCAST_(1) << 30)