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Searched refs:XTFPGA_CLKFRQ_VADDR (Results 1 – 3 of 3) sorted by relevance

/linux-4.1.27/arch/xtensa/platforms/xtfpga/
Dsetup.c104 *(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR); in update_clock_frequency()
180 clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR; in platform_calibrate_ccount()
317 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR; in xtavnet_init()
327 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR; in xtavnet_init()
/linux-4.1.27/arch/xtensa/platforms/xtfpga/include/platform/
Dserial.h16 #define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
Dhardware.h47 #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) macro