Searched refs:WORK2_REG (Results 1 - 1 of 1) sorted by relevance
| /linux-4.1.27/arch/arm/mach-lpc32xx/ |
| H A D | suspend.S | 19 #define WORK2_REG r1 define
56 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
57 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
58 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
61 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
62 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
63 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
69 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
70 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
76 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
77 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
78 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
89 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
90 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
95 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
96 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
112 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
113 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
134 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
135 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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Completed in 79 milliseconds