Searched refs:VIA_PCI_DMA_CSR0 (Results 1 – 3 of 3) sorted by relevance
| /linux-4.1.27/drivers/gpu/drm/via/ |
| D | via_dmablit.c | 215 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | in via_fire_dmablit()
221 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); in via_fire_dmablit()
222 VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04); in via_fire_dmablit()
294 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); in via_abort_dmablit()
302 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); in via_dmablit_engine_off()
333 ((status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); in via_dmablit_handler()
352 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); in via_dmablit_handler()
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| D | via_dmablit.h | 112 #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ macro
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| D | via_irq.c | 73 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
82 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
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