Searched refs:VCLK_SRC_SEL_MASK (Results 1 – 10 of 10) sorted by relevance
59 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()125 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
58 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
142 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
363 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
1576 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
158 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()236 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
1124 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()1197 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
7281 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()7355 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
919 #define VCLK_SRC_SEL_MASK 0x03 macro
1269 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()1329 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()