Searched refs:UTMIP_PLL_CFG1 (Results 1 – 4 of 4) sorted by relevance
125 #define UTMIP_PLL_CFG1 0x484 macro1000 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()1015 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()1024 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()1027 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
104 #define UTMIP_PLL_CFG1 0x484 macro1060 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()1075 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()1084 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()1087 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
129 #define UTMIP_PLL_CFG1 0x484 macro903 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()918 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()
88 #define UTMIP_PLL_CFG1 0x804 macro420 val = readl(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()425 writel(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()