Searched refs:UDC (Results 1 - 72 of 72) sorted by relevance

/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dpxa25x-udc.h5 #error "You can't include both PXA25x and PXA27x UDC support"
8 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
12 #define UDCCR __REG(0x40600000) /* UDC Control Register */
13 #define UDCCR_UDE (1 << 0) /* UDC enable */
14 #define UDCCR_UDA (1 << 1) /* UDC active */
22 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
33 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
46 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
59 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
70 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
82 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
94 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
119 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
130 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
141 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
152 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
H A Dpxa27x-udc.h5 #error You cannot include both PXA25x and PXA27x UDC support
8 #define UDCCR __REG(0x40600000) /* UDC Control Register */
17 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
19 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
21 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
28 #define UDCCR_UDR (1 << 2) /* UDC Resume */
29 #define UDCCR_UDA (1 << 1) /* UDC Active */
30 #define UDCCR_UDE (1 << 0) /* UDC Enable */
32 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
47 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
56 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
103 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
113 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
114 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
115 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
116 #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
117 #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
118 #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
119 #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
120 #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
121 #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
122 #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
123 #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
124 #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
125 #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
126 #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
127 #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
128 #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
129 #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
130 #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
131 #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
132 #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
133 #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
134 #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
135 #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
H A Deseries-gpio.h15 /* UDC GPIO definitions */
H A Dpalmtc.h41 /* UDC */
H A Dpxa3xx-regs.h178 #define CKEN_UDC 20 /* < UDC clock enable */
/linux-4.1.27/arch/arm/mach-ixp4xx/include/mach/
H A Dixp4xx-regs.h408 /* UDC Undocumented - Reserved1 */
410 /* UDC Undocumented - Reserved2 */
412 /* UDC Undocumented - Reserved3 */
414 /* UDC Control Register */
416 /* UDC Endpoint 0 Control/Status Register */
418 /* UDC Endpoint 1 (IN) Control/Status Register */
420 /* UDC Endpoint 2 (OUT) Control/Status Register */
422 /* UDC Endpoint 3 (IN) Control/Status Register */
424 /* UDC Endpoint 4 (OUT) Control/Status Register */
426 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
428 /* UDC Endpoint 6 (IN) Control/Status Register */
430 /* UDC Endpoint 7 (OUT) Control/Status Register */
432 /* UDC Endpoint 8 (IN) Control/Status Register */
434 /* UDC Endpoint 9 (OUT) Control/Status Register */
436 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
438 /* UDC Endpoint 11 (IN) Control/Status Register */
440 /* UDC Endpoint 12 (OUT) Control/Status Register */
442 /* UDC Endpoint 13 (IN) Control/Status Register */
444 /* UDC Endpoint 14 (OUT) Control/Status Register */
446 /* UDC Endpoint 15 (Interrupt) Control/Status Register */
448 /* UDC Frame Number Register High */
450 /* UDC Frame Number Register Low */
452 /* UDC Byte Count Reg 2 */
454 /* UDC Byte Count Reg 4 */
456 /* UDC Byte Count Reg 7 */
458 /* UDC Byte Count Reg 9 */
460 /* UDC Byte Count Reg 12 */
462 /* UDC Byte Count Reg 14 */
464 /* UDC Endpoint 0 Data Register */
466 /* UDC Endpoint 1 Data Register */
468 /* UDC Endpoint 2 Data Register */
470 /* UDC Endpoint 3 Data Register */
472 /* UDC Endpoint 4 Data Register */
474 /* UDC Endpoint 5 Data Register */
476 /* UDC Endpoint 6 Data Register */
478 /* UDC Endpoint 7 Data Register */
480 /* UDC Endpoint 8 Data Register */
482 /* UDC Endpoint 9 Data Register */
484 /* UDC Endpoint 10 Data Register */
486 /* UDC Endpoint 11 Data Register */
488 /* UDC Endpoint 12 Data Register */
490 /* UDC Endpoint 13 Data Register */
492 /* UDC Endpoint 14 Data Register */
494 /* UDC Endpoint 15 Data Register */
496 /* UDC Interrupt Control Register 0 */
498 /* UDC Interrupt Control Register 1 */
500 /* UDC Status Interrupt Register 0 */
502 /* UDC Status Interrupt Register 1 */
505 #define UDCCR_UDE (1 << 0) /* UDC enable */
506 #define UDCCR_UDA (1 << 1) /* UDC active */
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dpxa27x_udc.h26 #define UDCCR 0x0000 /* UDC Control Register */
27 #define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */
28 #define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */
29 #define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */
30 #define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */
31 #define UDCFNR 0x0014 /* UDC Frame Number Register */
32 #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
35 #define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */
36 #define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */
37 #define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */
38 #define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */
48 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
50 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
52 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
59 #define UDCCR_UDR (1 << 2) /* UDC Resume */
60 #define UDCCR_UDA (1 << 1) /* UDC Active */
61 #define UDCCR_UDE (1 << 0) /* UDC Enable */
173 * UDCCR = UDC Endpoint Configuration Registers
174 * UDCCSR = UDC Control/Status Register for this EP
175 * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo)
176 * UDCDR = UDC Endpoint Data Register (the fifo)
430 * @enabled: UDC was enabled by a previous udc_enable()
433 * @config: UDC active configuration
434 * @last_interface: UDC interface of the last SET_INTERFACE host request
435 * @last_alternate: UDC altsetting of the last SET_INTERFACE host request
H A Dpxa25x_udc.h29 #define UDCCFR UDC_RES2 /* UDC Control Function Register */
54 /* UDCCS = UDC Control/Status for this EP
55 * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
56 * UDDR = UDC Endpoint Data Register (the fifo)
H A Dudc-core.c2 * udc.c - Core UDC Framework
41 * This represents the internal data structure which is used by the UDC-class
198 * @udc: The UDC to be started
200 * This call is issued by the UDC Class driver when it's about
219 * This call is issued by the UDC Class driver after calling
223 * far as powering off UDC completely and disable its data
351 dev_dbg(&udc->dev, "unregistering UDC driver [%s]\n", usb_gadget_remove_driver()
402 dev_dbg(&udc->dev, "registering UDC driver [%s]\n", udc_bind_to_driver()
472 pr_debug("couldn't find an available UDC\n"); usb_gadget_probe_driver()
654 MODULE_DESCRIPTION("UDC Framework");
H A Damd5536udc.h2 * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
354 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
380 /* UDC CSR's */
489 /* UDC specific endpoint parameters */
H A Damd5536udc.c2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
31 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
114 * that UDC has only one bit (RDE) to enable/disable RX DMA for
177 /* Prints UDC device registers and endpoint irq registers */ print_regs()
354 /* ep ix in UDC CSR register space */ udc_ep_enable()
377 /* ep ix in UDC CSR register space */ udc_ep_enable()
380 /* set max packet size UDC CSR */ udc_ep_enable()
1461 /* Inits UDC context */ udc_basic_init()
1606 * Calls gadget with disconnect event and resets the UDC and makes
1670 /* Reset the UDC core */ udc_soft_reset()
1852 /* set max packet size of EP0 in UDC CSR */ activate_control_endpoints()
2342 * IN must not be handled (UDC defect) ? udc_data_in_isr()
2766 /* ep ix in UDC CSR register space */
2772 /* ep ix in UDC CSR register space */
2819 /* ep ix in UDC CSR register space */
2825 /* ep ix in UDC CSR register space */
2829 /* UDC CSR reg */
3326 DBG(dev, "UDC initiates remote wakeup\n"); udc_remote_wakeup()
H A Dpxa27x_udc.c2 * Handles the Intel 27x USB Device Controller (UDC)
40 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x
49 * This UDC hardware wants to implement a bit too much USB protocol. The
68 * made of UDC's double buffering either. USB "On-The-Go" is not implemented.
1291 * done from software on the PXA UDC, and the hardware pxa_ep_set_halt()
1544 * should_enable_udc - Tells if UDC should be enabled
1548 * The UDC should be enabled if :
1554 * Returns 1 if UDC should be enabled, 0 otherwise
1566 * should_disable_udc - Tells if UDC should be disabled
1570 * The UDC should be disabled if :
1575 * Returns 1 if UDC should be disabled
1738 * interrupts, sets usb as UDC client and setups endpoints.
1914 /* Tell UDC to enter Data Stage */ handle_ep0_ctrl_req()
2230 * irq_udc_suspend - Handle IRQ "UDC Suspend"
2245 * irq_udc_resume - Handle IRQ "UDC Resume"
2259 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration"
2284 * irq_udc_reset - Handle IRQ "UDC Reset"
2568 * Software must configure the USB OTG pad, UDC, and UHC pxa_udc_resume()
H A Dpxa25x_udc.c64 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
65 * series processors. The UDC for the IXP 4xx series is very similar.
74 * This UDC hardware wants to implement a bit too much USB protocol, so
79 * Note that the UDC hardware supports DMA (except on IXP) but that's
800 * done from software on the PXA UDC, and the hardware pxa25x_ep_set_halt()
924 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1197 /* until it's enabled, this UDC should be completely invisible
1213 * - enable UDC udc_enable()
H A Dr8a66597-udc.h2 * R8A66597 UDC
H A Domap_udc.c60 #define DRIVER_DESC "OMAP UDC driver"
67 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
71 * optional new "UDC not yet running" state to the gadget driver model,
513 * When DMA completion isn't request completion, the UDC continues with
2315 "UDC rev %d.%d, fifo mode %d, gadget %s\n" proc_udc_show()
2346 /* UDC controller registers */ proc_udc_show()
2768 INFO("OMAP UDC rev %d.%d%s\n", omap_udc_probe()
2841 ERR("unrecognized UDC HMC mode %d\n", hmc); omap_udc_probe()
H A Dfusb300_udc.h2 * Fusb300 UDC (USB gadget)
H A Dbcm63xx_udc.c2 * bcm63xx_udc.c -- BCM63xx UDC high/full speed USB device controller
1733 * Standard UDC gadget operations
2313 * bcm63xx_udc_probe - Initialize a new instance of the UDC.
H A Ddummy_hcd.c299 /* UDC suspend must cause a disconnect */ set_link_state_by_speed()
325 /* UDC suspend must cause a disconnect */ set_link_state_by_speed()
2634 pr_err("Number of emulated UDC must be in range of 1...%d\n",
H A Dm66592-udc.h2 * M66592 UDC (USB gadget)
H A Dlpc32xx_udc.c146 * Common UDC structure
2929 dev_err(udc->dev, "UDC already has a gadget driver\n"); lpc32xx_start()
3097 dev_err(udc->dev, "someone's using UDC memory\n"); lpc32xx_udc_probe()
H A Dfsl_qe_udc.c711 UDC transmit and receive process
2448 * UDC device Driver operation functions *
H A Dmv_udc_core.c2252 dev_err(&pdev->dev, "Request irq %d for UDC failed\n", mv_udc_probe()
2311 dev_info(&pdev->dev, "successful probe UDC device %s clock gating.\n", mv_udc_probe()
H A Dfotg210-udc.c2 * FOTG210 UDC Driver supports Bulk transfer so far
H A Dfusb300_udc.c2 * Fusb300 UDC (USB gadget)
H A Dgoku_udc.c1814 .device = 0x0107, /* this UDC */
H A Dm66592-udc.c2 * M66592 UDC (USB gadget)
H A Dr8a66597-udc.c2 * R8A66597 UDC (USB gadget)
H A Dat91_udc.c1879 /* request UDC and maybe VBUS irqs */ at91udc_probe()
H A Datmel_usba_udc.c2271 MODULE_DESCRIPTION("Atmel USBA UDC driver");
H A Dmv_u3d_core.c1159 * 2. UDC VBUS detect: we have to enable clock all the time. mv_u3d_vbus_session()
H A Dpch_udc.c2799 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n"); pch_udc_isr()
/linux-4.1.27/include/linux/platform_data/
H A Dmv_usb.h38 struct mv_usb_addon_irq *vbus; /* valid for OTG/UDC. VBUS change*/
H A Dpxa2xx_udc.h3 * USB Device Controller (UDC) is wired.
H A Dusb-s3c2410_udc.h24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
/linux-4.1.27/drivers/usb/isp1760/
H A Disp1760-udc.h51 * struct isp1760_udc - UDC state information
54 * regs: Base address of the UDC registers
H A Disp1760-udc.c97 * Called with the UDC spinlock held.
104 /* Called with the UDC spinlock held. */ isp1760_udc_ctrl_send_status()
125 /* Called without the UDC spinlock held. */ isp1760_udc_request_complete()
178 /* Called with the UDC spinlock held. */ isp1760_udc_receive()
1057 /* Called with the UDC spinlock held. */ isp1760_udc_connect()
1064 /* Called with the UDC spinlock held. */ isp1760_udc_disconnect()
1118 * reinitialize the UDC hardware. isp1760_udc_reset()
1205 dev_err(udc->isp->dev, "UDC already has a gadget driver\n"); isp1760_udc_start()
1214 dev_dbg(udc->isp->dev, "starting UDC with driver %s\n", isp1760_udc_start()
1227 dev_dbg(udc->isp->dev, "UDC started with driver %s\n", isp1760_udc_start()
1466 * by the UDC core. isp1760_udc_register()
H A Disp1760-core.c119 * If neither the HCD not the UDC is enabled return an error, as no isp1760_register()
/linux-4.1.27/arch/mips/alchemy/common/
H A Dusb.c6 * UDC here.
7 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
8 * as well as the PHY for EHCI and UDC.
39 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
45 #define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
46 #define USBCFG_DME (1 << 4) /* UDC mem enable */
75 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
298 * here at all: Port 2 routing (EHCI or UDC) must be set either au1300_usb_init()
337 if (!(r & USBCFG_UCE)) /* UDC also off? */ __au1200_ehci_control()
/linux-4.1.27/drivers/usb/chipidea/
H A Dci_hdrc_pci.c51 * @id: PCI hotplug ID connecting controller to UDC framework
55 * invokes the udc_probe() method to start the UDC associated with it
H A Dudc.h2 * udc.h - ChipIdea UDC structures
H A Dudc.c2 * udc.c - ChipIdea UDC driver
740 * @ci: UDC device
997 * @ci: UDC descriptor
1159 * @ci: UDC descriptor
1903 * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
/linux-4.1.27/arch/mips/pci/
H A Dfixup-lemote2f.c79 case 6: /* for UDC */ pcibios_map_irq()
124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ loongson_cs5536_ohci_fixup()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dpalmte2.c191 * UDC
338 if (!gpio_request(GPIO_NR_PALMTE2_USB_PULLUP, "UDC Vbus")) { palmte2_udc_init()
H A Deseries.c469 /* UDC */
665 /* UDC */
903 /* --------------------------- UDC definitions --------------------------- */
H A Dpalmtc.c306 * UDC palmtc_mkp_init()
H A Dpxa3xx.c51 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
H A Dvpac270.c126 /* UDC */
H A Dmioa701.c369 * USB UDC
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A Dirqs.h24 #define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */
H A DSA-1100.h76 * Universal Serial Bus (USB) Device Controller (UDC) control registers
80 * Controller (UDC) Control Register (read/write).
82 * Controller (UDC) Address Register (read/write).
84 * Controller (UDC) Output Maximum Packet size register
87 * Controller (UDC) Input Maximum Packet size register
90 * Controller (UDC) Control/Status register end-point 0
93 * Controller (UDC) Control/Status register end-point 1
96 * Controller (UDC) Control/Status register end-point 2
99 * Controller (UDC) Data register end-point 0
102 * Controller (UDC) Write Count register end-point 0
105 * Controller (UDC) Data Register (read/write).
107 * Controller (UDC) Status Register (read/write).
110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
120 #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
122 #define UDCCR_UDD 0x00000001 /* UDC Disable */
123 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
1265 #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
/linux-4.1.27/arch/arm/mach-omap1/
H A Dusb.c45 * - 5912 OSK UDC, with *nonstandard* A-to-A cable
46 * - 1510 Innovator UDC with bundled usb0 cable
135 pr_debug("can't register UDC device, %d\n", status); omap_otg_init()
610 pr_debug("can't register UDC device, %d\n", status); omap_1510_usb_init()
/linux-4.1.27/drivers/usb/musb/
H A Djz4740.c87 pr_err("HS UDC: no transceiver configured\n"); jz4740_musb_init()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dmach-qt2410.c289 /* UDC */
H A Dmach-mini2440.c100 /* USB device UDC support */
/linux-4.1.27/drivers/clk/pxa/
H A Dclk-pxa3xx.c148 PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
/linux-4.1.27/drivers/usb/phy/
H A Dphy-gpio-vbus-usb.c32 * Needs to be loaded before the UDC driver that will use it.
H A Dphy-isp1301-omap.c936 /* UDC driver just set OTG_BSESSVLD */ b_peripheral()
1041 /* UDC driver will clear OTG_BSESSVLD */ isp_update_otg()
/linux-4.1.27/include/linux/usb/
H A Dgadget.h152 * endpoint. It's set once by UDC driver when endpoint is initialized, and
193 * This function should be used only in UDC drivers to initialize endpoint
506 * @max_speed: Maximal speed the UDC can handle. UDC must support this
/linux-4.1.27/drivers/usb/gadget/function/
H A Df_sourcesink.c403 * We still want to work even if the UDC doesn't have isoc sourcesink_bind()
422 * give parameters that their UDC doesn't support. sourcesink_bind()
444 * give parameters that their UDC doesn't support. sourcesink_bind()
H A Df_ecm.c491 /* REVISIT locking of cdc_filter. This assumes the UDC ecm_setup()
H A Df_uvc.c618 * give parameters that their UDC doesn't support. uvc_function_bind()
H A Df_ncm.c638 * REVISIT locking of cdc_filter. This assumes the UDC ncm_setup()
H A Df_fs.c218 * UDC layer requires to provide a buffer even for ZLP, but should __ffs_ep0_queue_wait()
H A Df_mass_storage.c2449 * bulk endpoint, clear the halt now. (The SuperH UDC handle_exception()
/linux-4.1.27/drivers/usb/gadget/
H A Dconfigfs.c295 GI_DEVICE_DESC_ITEM_ATTR(UDC); variable
436 * bound to an UDC. Since this isn't possible at the moment, we simply config_usb_cfg_unlink()
/linux-4.1.27/drivers/scsi/sym53c8xx_2/
H A Dsym_defs.h266 #define UDC 0x04 /* sta: unexpected disconnect */ macro
H A Dsym_hipd.c1865 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); sym_start_up()
2772 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
2775 * - Some combinations of STO, PAR, UDC, ...
2791 * then UDC happenning before the CPU have restarted
2793 * same command on UDC, since the SCRIPTS didn't restart
2904 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && sym_interrupt()
2922 * On STO and UDC, we complete the CCB with the corres- sym_interrupt()
2938 else if (sist & UDC) sym_int_udc (np); sym_interrupt()
/linux-4.1.27/drivers/scsi/
H A Dncr53c8xx.h788 #define UDC 0x04 /* sta: unexpected disconnect */ macro
H A Dncr53c8xx.c5315 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); ncr_init()
5893 ** IID and/or UDC.
5958 if (!(sist & (STO|GEN|HTH|SGE|UDC|RST)) && ncr_exception()
5993 ** interrupts may occur at the same time (UDC, IID), so ncr_exception()
6025 ** We are more soft for UDC. ncr_exception()
6055 if (sist & UDC) { ncr_exception()
H A Datari_NCR5380.c1140 pr_err("scsi%d: overrun in UDC counter -- not prepared to deal with this!\n", NCR5380_dma_complete()
/linux-4.1.27/drivers/staging/emxx_udc/
H A Demxx_udc.c47 #define DRIVER_DESC "EMXX UDC driver"
/linux-4.1.27/drivers/usb/host/
H A Disp1362-hcd.c43 * The PXA255 UDC apparently doesn't handle GET_STATUS, GET_CONFIG and

Completed in 1724 milliseconds