/linux-4.1.27/arch/arm/mach-mmp/include/mach/ |
H A D | uncompress.h | 17 volatile unsigned long *UART; variable 21 /* UART enabled? */ putc() 22 if (!(UART[UART_IER] & UART_IER_UUE)) putc() 25 while (!(UART[UART_LSR] & UART_LSR_THRE)) putc() 28 UART[UART_TX] = c; putc() 41 UART = (unsigned long *)UART2_BASE; arch_decomp_setup() 44 UART = (unsigned long *)UART3_BASE; arch_decomp_setup()
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/linux-4.1.27/include/linux/ |
H A D | altera_uart.h | 2 * altera_uart.h -- Altera UART driver defines. 11 unsigned int uartclk; /* UART clock rate */
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H A D | altera_jtaguart.h | 2 * altera_jtaguart.h -- Altera JTAG UART driver defines.
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H A D | serial_bcm63xx.h | 4 /* UART Control Register */ 41 /* UART Baudword register */ 44 /* UART Misc Control register */ 59 /* UART External Input Configuration register */ 84 /* UART Interrupt register */ 105 /* UART Fifo register */
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H A D | sunserialcore.h | 8 * Port to new UART layer is:
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H A D | serial_max3100.h | 17 * struct plat_max3100 - MAX3100 SPI UART platform data
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H A D | ti_wilink_st.h | 32 * common physical interface like UART. 59 * id is nothing but the 1st byte of the packet in UART frame. 64 * how much to receive, if the data is split across UART frames. 239 * the ldisc by opening UART when protocol drivers register. 345 * the change baud rate of host-side UART, which 421 * @dev_name: The UART/TTY name to which chip is interfaced. (eg: /dev/ttyS1) 422 * @flow_cntrl: Should always be 1, since UART's CTS/RTS is used for PM 424 * @baud_rate: The baud rate supported by the Host UART controller, this will 435 * specific board-xx.c to take actions such as cut UART clocks when chip
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/linux-4.1.27/arch/cris/include/asm/ |
H A D | serial.h | 5 * This assumes you have a 1.8432 MHz clock for your UART.
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/linux-4.1.27/arch/arm/mach-sa1100/include/mach/ |
H A D | uncompress.h | 20 #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) macro 28 if (UART(UTCR3) & UTCR3_TXE) break; putc() 30 if (UART(UTCR3) & UTCR3_TXE) break; putc() 32 if (UART(UTCR3) & UTCR3_TXE) break; putc() 36 /* wait for space in the UART's transmitter */ putc() 37 while (!(UART(UTSR1) & UTSR1_TNF)) putc() 41 UART(UTDR) = c; putc()
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H A D | SA-1100.h | 191 * Universal Asynchronous Receiver/Transmitter (UART) control registers 195 * Receiver/Transmitter (UART) Control Register 0 198 * Receiver/Transmitter (UART) Control Register 1 201 * Receiver/Transmitter (UART) Control Register 2 204 * Receiver/Transmitter (UART) Control Register 3 207 * Receiver/Transmitter (UART) Data Register 210 * Receiver/Transmitter (UART) Status Register 0 213 * Receiver/Transmitter (UART) Status Register 1 (read). 216 * Receiver/Transmitter (UART) Control Register 0 219 * Receiver/Transmitter (UART) Control Register 1 222 * Receiver/Transmitter (UART) Control Register 2 225 * Receiver/Transmitter (UART) Control Register 3 228 * Receiver/Transmitter (UART) Control Register 4 231 * Receiver/Transmitter (UART) Data Register 234 * Receiver/Transmitter (UART) Status Register 0 237 * Receiver/Transmitter (UART) Status Register 1 (read). 240 * Receiver/Transmitter (UART) Control Register 0 243 * Receiver/Transmitter (UART) Control Register 1 246 * Receiver/Transmitter (UART) Control Register 2 249 * Receiver/Transmitter (UART) Control Register 3 252 * Receiver/Transmitter (UART) Data Register 255 * Receiver/Transmitter (UART) Status Register 0 258 * Receiver/Transmitter (UART) Status Register 1 (read). 263 * fua, Tua Frequency, period of the UART communication. 266 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ 267 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ 268 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ 269 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ 270 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ 271 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ 272 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ 273 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ 275 #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ 276 #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ 277 #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ 278 #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ 279 #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ 280 #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ 281 #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ 283 #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ 284 #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ 285 #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ 286 #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ 287 #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ 288 #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ 289 #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ 290 #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ 292 #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ 293 #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ 294 #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ 295 #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ 296 #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ 297 #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ 298 #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ 437 #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ 439 #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ 550 #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ 1197 #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ 1198 #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ 1201 #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ 1205 #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ 1267 #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ 1269 #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ 1337 #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ 1338 #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ 1343 #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ 1344 #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ 1355 #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ 1356 #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ 1357 #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ 1368 #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ 1369 #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ 1372 #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ 1373 #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
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H A D | irqs.h | 26 #define IRQ_Ser1UART 16 /* Ser. port 1 UART */ 28 #define IRQ_Ser3UART 18 /* Ser. port 3 UART */
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/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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H A D | irq.h | 20 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */ 28 #define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */ 29 #define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
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H A D | anomaly.h | 42 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 88 /* UART TX Interrupt Masked Erroneously */ 92 /* Incorrect Pulse-Width of UART Start Bit */ 98 /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ 100 /* UART STB Bit Incorrectly Affects Receiver Setting */ 186 /* UART Break Signal Issues */ 242 /* Timer Auto-Baud Mode requires the UART clock to be enabled. */
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/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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H A D | irq.h | 55 #define IRQ_UART0_ERROR 48 /* UART Error Interrupt */ 56 #define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
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H A D | anomaly.h | 112 /* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ 130 /* UART Gets Disabled after UART Boot */
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/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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H A D | irq.h | 25 #define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */ 52 #define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */ 53 #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ 54 #define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */ 55 #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
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H A D | anomaly.h | 26 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 98 /* UART TX Interrupt Masked Erroneously */ 104 /* Incorrect Pulse-Width of UART Start Bit */ 108 /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ 110 /* UART STB Bit Incorrectly Affects Receiver Setting */ 218 /* UART Break Signal Issues */
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/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/ |
H A D | bfin_serial.h | 2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
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/linux-4.1.27/arch/arm/mach-iop32x/include/mach/ |
H A D | glantank.h | 10 #define GLANTANK_UART 0xfe800000 /* UART */
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H A D | n2100.h | 10 #define N2100_UART 0xfe800000 /* UART */
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H A D | iq31244.h | 10 #define IQ31244_UART 0xfe800000 /* UART #1 */
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H A D | iq80321.h | 10 #define IQ80321_UART 0xfe800000 /* UART #1 */
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/linux-4.1.27/arch/tile/include/gxio/ |
H A D | uart.h | 25 * An API for manipulating UART interface. 30 * The Rshim allows access to the processor's UART interface. 33 /* A context object used to manage UART resources. */ 44 /* Request UART interrupts. 46 * Request that interrupts be delivered to a tile when the UART's 55 * @return Zero if all of the requested UART events were successfully 63 /* Initialize a UART context. 70 * @param uart_index Index of the UART to use. 76 /* Destroy a UART context. 90 /* Write UART register. 92 * @param offset UART register offset. 93 * @param word Data will be wrote to UART reigister. 98 /* Read UART register. 100 * @param offset UART register offset. 101 * @return Data read from UART register.
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/linux-4.1.27/include/uapi/linux/ |
H A D | serial_core.h | 44 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ 45 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ 46 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ 47 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ 48 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */ 49 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */ 50 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */ 54 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ 55 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ 56 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ 57 #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ 58 #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ 168 /* MN10300 on-chip UART numbers */ 185 /* Timberdale UART */ 207 /* High Speed UART for Medfield */ 210 /* TI OMAP-UART */ 216 /* Cadence (Xilinx Zynq) UART */ 225 /* ARC (Synopsys) on-chip UART */ 240 /* Tilera TILE-Gx UART */ 243 /* MEN 16z135 UART */
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H A D | tty.h | 27 #define N_HCI 15 /* Bluetooth HCI UART */
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H A D | tty_flags.h | 20 #define ASYNCB_SKIP_TEST 6 /* Skip UART test during autoconfiguration */ 29 #define ASYNCB_BUGGY_UART 14 /* This is a buggy UART, skip some safety
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H A D | serial_reg.h | 9 * These are the UART port assignments, expressed as offsets from the base 233 #define UART_IER_UUE 0x40 /* UART Unit Enable */ 349 #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ 351 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ 352 #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
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H A D | cyclades.h | 45 *UART error signaling 167 __u32 uart_irq_status; /* UART IRQ status Register */ 174 __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ 176 __u32 uart_wait_state; /* UART wait-state Register */ 326 #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ 327 #define C_FS_SENDING 0x00000001 /* UART is sending data */
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/linux-4.1.27/arch/arm/include/debug/ |
H A D | tegra.S | 59 /* Test UART's reset bit */ \ 61 /* If set, can't use UART; jump to save no UART */ \ 67 /* Test UART's clock enable bit */ \ 69 /* If clear, can't use UART; jump to save no UART */ \ 71 /* Passed all tests, load address of UART registers */ \ 73 /* Jump to save UART address */ \ 94 cmp \rv, #2 @ 2 and 3 mean DCC, UART 98 11: lsr \rv, \rp, #15 @ 17:15 are UART ID 100 cmp \rv, #0 @ UART 0? 102 cmp \rv, #1 @ UART 1? 104 cmp \rv, #2 @ UART 2? 106 cmp \rv, #3 @ UART 3? 108 cmp \rv, #4 @ UART 4? 115 /* Check UART A validity */ 121 /* Check UART B validity */ 127 /* Check UART C validity */ 133 /* Check UART D validity */ 139 /* Check UART E validity */ 144 /* No valid UART found */ 148 /* Record whichever UART we chose */ 150 cmp \rp, #0 @ Valid UART address? 164 /* Load previously selected UART address */ 171 * check to make sure that the UART address is actually valid. 206 * want a single copy of the data. In particular, the UART probing code above 220 /* Debug UART initialization required */ 222 /* Debug UART physical address */ 224 /* Debug UART virtual address */
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H A D | exynos.S | 17 /* note, for the boot process to work we have to keep the UART 19 * mapping the head code makes. We keep the UART virtual address
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H A D | s5pv210.S | 16 /* note, for the boot process to work we have to keep the UART 18 * mapping the head code makes. We keep the UART virtual address
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H A D | vexpress.S | 30 @ should use UART at 0x10009000 31 @ - all other (RS1 complaint) tiles use UART mapped
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H A D | sti.S | 31 #error "DEBUG UART is not Configured"
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H A D | ux500.S | 14 #error Invalid Ux500 debug UART
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/linux-4.1.27/arch/tile/include/hv/ |
H A D | drv_uart_intf.h | 16 * Interface definitions for the UART driver. 24 /** Number of UART ports supported. */ 27 /** The mmap file offset (PA) of the UART MMIO region. */
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/linux-4.1.27/arch/arm/mach-gemini/include/mach/ |
H A D | uncompress.h | 19 static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE; variable 28 while (!(UART[UART_LSR] & UART_LSR_THRE)) putc() 30 UART[UART_TX] = c; putc()
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H A D | hardware.h | 65 * UART Clock when System clk is 150MHz
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/linux-4.1.27/arch/x86/include/asm/ |
H A D | serial.h | 5 * This assumes you have a 1.8432 MHz clock for your UART. 23 /* UART CLK PORT IRQ FLAGS */ \
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/linux-4.1.27/arch/alpha/include/asm/ |
H A D | serial.h | 7 * This assumes you have a 1.8432 MHz clock for your UART. 25 /* UART CLK PORT IRQ FLAGS */ \
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/linux-4.1.27/drivers/tty/serial/8250/ |
H A D | 8250.h | 72 #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */ 73 #define UART_CAP_EFR (1 << 9) /* UART has EFR */ 74 #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */ 76 #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */ 77 #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */ 78 #define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */ 81 #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */ 82 #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ 83 #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */ 84 #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ 85 #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
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H A D | 8250_pci.c | 159 * with 3 UARTs (the third UART on the second chip is unused). Superdome 265 * high, and have 2 UART chips, both ints must be pci_plx9050_init() 401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ sbs_init() 430 * the UART clocking frequency. Each UART can be clocked independently 433 * version of serial driver doesn't support differently clocked UART's 435 * high frequency clocking for all UART's on given card. It is safe (I 450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 492 /* Change clock frequency for the first UART. */ pci_siig20x_init() 496 /* If this card has 2 UART, we have to do the same with second UART. */ pci_siig20x_init() 742 /* UART Port Control Register */ 973 /* activate the UART (UARTx_En) */ pci_ite887x_init() 975 /* write new config with activated UART */ pci_ite887x_init() 1748 /* Enable UART I/O port */ pci_fintek_init() 1754 /* LSB UART */ pci_fintek_init() 1758 /* MSB UART */ pci_fintek_init() 3074 * reg_shift - describes how the UART registers are mapped 3077 * offset 0x10 from the UART base, while UART_IER is defined as 1 3688 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3758 * PA Semi PWRficient PA6T-1682M on-chip UART 3910 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4647 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4650 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4653 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4656 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4659 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4662 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4665 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4668 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4671 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4674 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4677 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4680 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4683 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4686 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4689 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4692 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4695 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4698 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4701 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4704 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4707 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4710 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4713 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4716 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4719 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4722 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4725 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4728 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4731 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4734 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4737 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4740 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4743 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4746 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4749 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4752 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4755 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4758 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4761 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4764 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4767 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4770 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4773 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4776 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 5163 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 5201 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5368 * PA Semi PA6T-1682M on-chip UART
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H A D | 8250_fsl.c | 7 * Freescale 16550 UART "driver", Copyright (C) 2011 Paul Gortmaker.
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/linux-4.1.27/include/linux/platform_data/ |
H A D | dma-hsu.h | 2 * Driver for the High Speed UART DMA
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H A D | serial-omap.h | 2 * Driver for OMAP-UART controller. 35 unsigned int uartclk; /* UART clock rate */
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H A D | sa11x0-serial.h | 6 * Low level machine dependent UART functions.
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H A D | dma-imx.h | 24 IMX_DMATYPE_UART, /* MCU domain UART */ 25 IMX_DMATYPE_UART_SP, /* Shared UART */
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/linux-4.1.27/arch/avr32/include/asm/ |
H A D | serial.h | 5 * This assumes you have a 1.8432 MHz clock for your UART.
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/linux-4.1.27/arch/ia64/include/asm/ |
H A D | serial.h | 6 * This assumes you have a 1.8432 MHz clock for your UART.
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/linux-4.1.27/arch/openrisc/include/asm/ |
H A D | serial.h | 26 /* There's a generic version of this file, but it assumes a 1.8MHz UART clk... 27 * this, on the other hand, assumes the UART clock is tied to the system
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/linux-4.1.27/arch/m68k/include/asm/ |
H A D | serial.h | 11 * This assumes you have a 1.8432 MHz clock for your UART. 30 /* UART CLK PORT IRQ FLAGS */ \
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H A D | m5206sim.h | 141 #define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ 142 #define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
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H A D | m5272sim.h | 107 #define MCF_IRQ_UART0 73 /* UART 0 */ 108 #define MCF_IRQ_UART1 74 /* UART 1 */
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H A D | m5407sim.h | 115 #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 116 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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H A D | m54xxsim.h | 32 * UART module.
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H A D | MC68328.h | 267 #define UART_IRQ_NUM 2 /* UART interrupt */ 298 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ 332 #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 362 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 396 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 859 * 0xFFFFF9xx -- UART 864 * UART Status/Control Register 884 #define USTCNT_UARTEN 0x8000 /* UART Enable */ 900 * UART Baud Control Register 916 * UART Receiver Register 935 * UART Transmitter Register 958 * UART Miscellaneous Register
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H A D | MC68EZ328.h | 230 #define UART_IRQ_NUM 2 /* UART interrupt */ 256 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ 285 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 314 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 667 * 0xFFFFF9xx -- UART 672 * UART Status/Control Register 692 #define USTCNT_UEN 0x8000 /* UART Enable */ 708 * UART Baud Control Register 721 * UART Receiver Register 741 * UART Transmitter Register 765 * UART Miscellaneous Register 784 * UART Non-integer Prescaler Register
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H A D | m5307sim.h | 117 * UART module. 151 #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 152 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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H A D | mcfuart.h | 4 * mcfuart.h -- ColdFire internal UART support defines. 22 unsigned int uartclk; /* UART clock rate */ 26 * Define the ColdFire UART register set addresses.
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H A D | MC68VZ328.h | 233 #define UART1_IRQ_NUM 2 /* UART 1 interrupt */ 243 #define UART2_IRQ_NUM 12 /* UART 2 interrupt */ 266 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ 295 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 324 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ 760 * 0xFFFFF9xx -- UART 765 * UART Status/Control Register 786 #define USTCNT_UEN 0x8000 /* UART Enable */ 802 * UART Baud Control Register 815 * UART Receiver Register 835 * UART Transmitter Register 859 * UART Miscellaneous Register 878 * UART Non-integer Prescaler Register
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H A D | m525xsim.h | 100 * UART module. 147 #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 148 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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/linux-4.1.27/arch/m68k/include/uapi/asm/ |
H A D | bootinfo-hp300.h | 14 #define BI_HP300_UART_SCODE 0x8001 /* UART select code (__be32) */ 15 #define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (__be32) */
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/linux-4.1.27/arch/arm/mach-exynos/include/mach/ |
H A D | map.h | 18 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400. 39 /* Compatibility UART */
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/linux-4.1.27/arch/mips/mti-malta/ |
H A D | malta-platform.c | 13 * 1. Probe driver for the Malta's UART ports: 16 * o 1 port in the CBUS UART, a discrete 16550 which normally is only used 20 * UART becoming ttyS0. 52 .mapbase = 0x1f000900, /* The CBUS UART */
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/linux-4.1.27/arch/arm/mach-realview/include/mach/ |
H A D | board-eb.h | 29 #define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */ 30 #define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */ 31 #define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */ 32 #define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */
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H A D | board-pba8.h | 29 #define REALVIEW_PBA8_UART0_BASE 0x10009000 /* UART 0 */ 30 #define REALVIEW_PBA8_UART1_BASE 0x1000A000 /* UART 1 */ 31 #define REALVIEW_PBA8_UART2_BASE 0x1000B000 /* UART 2 */ 32 #define REALVIEW_PBA8_UART3_BASE 0x1000C000 /* UART 3 */
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H A D | board-pb1176.h | 29 #define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */ 46 #define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */ 47 #define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */ 48 #define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */ 49 #define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */
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H A D | irqs-pb1176.h | 45 #define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ 46 #define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ 47 #define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ 48 #define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */ 61 #define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */
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H A D | board-pb11mp.h | 29 #define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */ 30 #define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */ 31 #define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */ 32 #define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */
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H A D | board-pbx.h | 28 #define REALVIEW_PBX_UART0_BASE 0x10009000 /* UART 0 */ 29 #define REALVIEW_PBX_UART1_BASE 0x1000A000 /* UART 1 */ 30 #define REALVIEW_PBX_UART2_BASE 0x1000B000 /* UART 2 */ 31 #define REALVIEW_PBX_UART3_BASE 0x1000C000 /* UART 3 */
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H A D | irqs-pb11mp.h | 77 #define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */ 78 #define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */ 79 #define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */ 80 #define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
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H A D | irqs-pba8.h | 41 #define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */ 42 #define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */ 43 #define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */ 44 #define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
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H A D | irqs-pbx.h | 40 #define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */ 41 #define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */ 42 #define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */ 43 #define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */
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H A D | irqs-eb.h | 41 #define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ 42 #define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ 43 #define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ 44 #define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
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H A D | uncompress.h | 35 * Return the UART base address
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/linux-4.1.27/arch/arm/plat-samsung/include/plat/ |
H A D | irq-uart.h | 6 * Header file for Samsung SoC UART IRQ demux for S3C64XX and later
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H A D | pm-common.h | 45 * struct pm_uart_save - save block for core UART 52 * Save block for UART registers to be held over sleep and restored if they 77 * @base: Virtual base of UART to use for suspend/resume debugging. 80 * UART port base address and configuration.
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H A D | map-base.h | 38 #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
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H A D | map-s3c.h | 38 * it is the same distance apart from the UART in the
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/linux-4.1.27/arch/tile/gxio/ |
H A D | uart.c | 16 * Implementation of UART gxio calls. 72 /* UART register write wrapper. */ gxio_uart_write() 81 /* UART register read wrapper. */ gxio_uart_read()
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/linux-4.1.27/drivers/media/pci/mantis/ |
H A D | mantis_uart.c | 82 dprintk(MANTIS_ERROR, 1, "UART framing error"); mantis_uart_read() 86 dprintk(MANTIS_ERROR, 1, "UART parity error"); mantis_uart_read() 104 dprintk(MANTIS_INFO, 1, "UART BUF:%d <%02x> ", i, buf[i]); mantis_uart_work() 151 dprintk(MANTIS_INFO, 1, "Initializing UART @ %sbps parity:%s", mantis_uart_init() 176 dprintk(MANTIS_DEBUG, 1, "UART successfully initialized"); mantis_uart_init()
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H A D | mantis_core.c | 152 dprintk(verbose, MANTIS_DEBUG, 1, "Mantis UART init failed"); mantis_core_init() 165 dprintk(verbose, MANTIS_ERROR, 1, "UART exit failed"); mantis_core_exit()
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/linux-4.1.27/arch/mips/include/asm/ |
H A D | nile4.h | 161 #define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ 162 #define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ 163 #define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ 164 #define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ 165 #define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ 166 #define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ 167 #define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ 168 #define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ 169 #define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ 170 #define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ 171 #define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ 172 #define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ 185 #define NILE4_INT_UART 4 /* UART Interrupt */
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/linux-4.1.27/arch/mips/include/asm/sn/sn0/ |
H A D | hubmd.h | 64 #define MD_UREG0_0 0x220000 /* uController/UART 0 register */ 65 #define MD_UREG0_1 0x220008 /* uController/UART 0 register */ 66 #define MD_UREG0_2 0x220010 /* uController/UART 0 register */ 67 #define MD_UREG0_3 0x220018 /* uController/UART 0 register */ 68 #define MD_UREG0_4 0x220020 /* uController/UART 0 register */ 69 #define MD_UREG0_5 0x220028 /* uController/UART 0 register */ 70 #define MD_UREG0_6 0x220030 /* uController/UART 0 register */ 71 #define MD_UREG0_7 0x220038 /* uController/UART 0 register */ 73 #define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */ 77 #define MD_UREG1_0 0x220080 /* uController/UART 1 register */ 78 #define MD_UREG1_1 0x220088 /* uController/UART 1 register */ 79 #define MD_UREG1_2 0x220090 /* uController/UART 1 register */ 80 #define MD_UREG1_3 0x220098 /* uController/UART 1 register */ 81 #define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */ 82 #define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */ 83 #define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */ 84 #define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */ 85 #define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */ 86 #define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */ 87 #define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */ 88 #define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */ 89 #define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */ 90 #define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */ 91 #define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ 92 #define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
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H A D | addrs.h | 251 #define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */ 252 #define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */ 253 #define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
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/linux-4.1.27/arch/mips/pmcs-msp71xx/ |
H A D | msp_serial.c | 73 * The DesignWare APB UART has an Busy Detect (0x07) interrupt msp_serial_handle_irq() 74 * meaning an LCR write attempt occurred while the UART was msp_serial_handle_irq() 75 * busy. The interrupt must be cleared by reading the UART msp_serial_handle_irq() 78 * Note: MSP reserves 0x20 bytes of address space for the UART msp_serial_handle_irq() 80 * 0xc0 from the start of the UART. msp_serial_handle_irq() 104 ppfinit("UART clock set to %d\n", uartclk); msp_serial_setup()
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/linux-4.1.27/arch/mips/include/asm/mach-loongson/ |
H A D | irq.h | 11 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
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/linux-4.1.27/include/sound/ |
H A D | mpu401.h | 29 #define MPU401_HW_SB 2 /* SoundBlaster MPU-401 UART */ 30 #define MPU401_HW_ES1688 3 /* AudioDrive ES1688 MPU-401 UART */ 34 #define MPU401_HW_ES18XX 7 /* AudioDrive ES18XX MPU-401 UART */ 42 #define MPU401_HW_CMIPCI 15 /* CMIPCI MPU-401 UART */
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/linux-4.1.27/arch/mips/kernel/ |
H A D | 8250-platform.c | 46 MODULE_DESCRIPTION("Generic 8250 UART probe driver");
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/linux-4.1.27/arch/arm/mach-s3c64xx/include/mach/ |
H A D | pm-core.h | 28 * that the resume settings for the UART are suitable for the s3c_pm_debug_init_uart() 72 /* S3C64XX UART blocks only support level interrupts, so ensure that s3c_pm_arch_update_uart() 73 * when we restore unused UART blocks we force the level interrupt s3c_pm_arch_update_uart() 77 /* We have a constraint on changing the clock type of the UART s3c_pm_arch_update_uart()
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/linux-4.1.27/arch/arm/mach-davinci/include/mach/ |
H A D | serial.h | 26 /* DaVinci UART register offsets */
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/linux-4.1.27/arch/arm/mach-lpc32xx/ |
H A D | serial.c | 79 /* UART clocks are off, let clock driver manage them */ lpc32xx_serial_init() 88 /* Setup UART clock modes for all UARTs, disable autoclock */ lpc32xx_serial_init() 91 /* pre-UART clock divider set to 1 */ lpc32xx_serial_init() 108 /* This needs to be done after all UART clocks are setup */ lpc32xx_serial_init()
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/linux-4.1.27/arch/mips/cobalt/ |
H A D | serial.c | 2 * Registration of Cobalt UART platform device. 59 * Cobalt Qube1 has no UART. cobalt_uart_add()
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/linux-4.1.27/arch/arm/mach-omap1/include/mach/ |
H A D | serial.h | 17 * Memory entry used for the DEBUG_LL UART configuration, relative to 20 * Note that using a memory location for storing the UART configuration
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H A D | uncompress.h | 53 /* Check for UART 16x mode */ putc() 67 * Macros to configure UART1 and debug UART
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/linux-4.1.27/arch/arm/mach-pxa/include/mach/ |
H A D | mainstone.h | 53 #define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ 54 #define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ 86 #define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ 87 #define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ 88 #define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */
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H A D | regs-uart.h | 8 /* Full Function UART (FFUART) */ 24 /* Bluetooth UART (BTUART) */ 40 /* Standard UART (STUART) */ 56 /* Hardware UART (HWUART) */ 76 #define IER_UUE (1 << 6) /* UART Unit Enable */
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H A D | palmtc.h | 50 /* UART */
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/linux-4.1.27/arch/arm/mach-omap1/ |
H A D | serial.c | 55 UART_OMAP_MDR1_DISABLE); /* disable UART */ omap_serial_reset() 58 UART_OMAP_MDR1_16X_MODE); /* enable UART */ omap_serial_reset() 220 ret = gpio_request(gpio_nr, "UART wake"); omap_serial_set_port_wakeup() 222 printk(KERN_ERR "Could not request UART wake GPIO: %i\n", omap_serial_set_port_wakeup() 231 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n", omap_serial_set_port_wakeup()
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/linux-4.1.27/drivers/tty/serial/ |
H A D | mcf.c | 4 * mcf.c -- Freescale ColdFire UART driver 159 /* Reset UART, get it into known state... */ mcf_startup() 163 /* Enable the UART transmitter and receiver */ mcf_startup() 189 /* Disable UART transmitter and receiver */ mcf_shutdown() 261 dev_dbg(port->dev, "Setting UART to RS485\n"); mcf_set_termios() 402 if (request_irq(port->irq, mcf_interrupt, 0, "UART", port)) mcf_config_port() 403 printk(KERN_ERR "MCF: unable to attach ColdFire UART %d " mcf_config_port() 411 return (port->type == PORT_MCF) ? "ColdFire UART" : NULL; mcf_type() 449 dev_dbg(port->dev, "Setting UART to RS485\n"); mcf_config_rs485() 453 dev_dbg(port->dev, "Setting UART to RS232\n"); mcf_config_rs485() 604 * Define the mcf UART driver structure. 678 printk("ColdFire internal UART serial driver\n"); mcf_init() 705 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
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H A D | ucc_uart.c | 2 * Freescale QUICC Engine UART device driver 11 * This driver adds support for UART devices via Freescale's QUICC Engine 14 * If Soft-UART support is needed but not already present, then this driver 15 * will request and upload the "Soft-UART" microcode upon probe. The 40 * The GUMR flag for Soft UART. This would normally be defined in qe.h, 41 * but Soft-UART is a hack and we want to keep everything related to it in 44 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ 47 * soft_uart is 1 if we need to use Soft-UART mode 61 * UART, we have major number 204 and minor numbers 46 - 49, which are the 101 __be16 uaddr[2]; /* UART address character 1 & 2 */ 120 /* The rest is for Soft-UART only */ 132 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ 140 /* SUPSMR definitions, for Soft-UART only */ 644 * Initialize a UCC for UART. 646 * This function configures a given UCC to be used as a UART device. Basic 648 * does all the UART-specific stuff. 661 /* Program the UCC UART parameter RAM */ qe_uart_init_ucc() 678 /* Configure the GUMR registers for UART */ qe_uart_init_ucc() 680 /* Soft-UART requires a 1X multiplier for TX */ qe_uart_init_ucc() 728 /* Soft-UART requires TX to be 1X */ qe_uart_init_ucc() 735 /* Set UART mode. qe_uart_init_ucc() 741 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). qe_uart_init_ucc() 785 * If we're using Soft-UART mode, then we need to make sure the qe_uart_startup() 789 dev_err(port->dev, "Soft-UART firmware not uploaded\n"); qe_uart_startup() 966 /* Soft-UART requires a 1X multiplier for TX */ qe_uart_set_termios() 1084 /* UART operations 1203 * Determine if we need Soft-UART mode ucc_uart_probe() 1206 dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); ucc_uart_probe() 1211 * If we are using Soft-UART, determine if we need to upload the ucc_uart_probe() 1220 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { ucc_uart_probe() 1314 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); ucc_uart_probe() 1333 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); ucc_uart_probe() 1501 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n"); ucc_uart_init() 1508 printk(KERN_ERR "ucc-uart: could not register UART driver\n"); ucc_uart_init() 1525 "Freescale QUICC Engine UART device driver unloading\n"); ucc_uart_exit() 1534 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
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H A D | men_z135_uart.c | 2 * MEN 16z135 High Speed UART 136 * @uart: The UART port 158 * @uart: The UART port 180 * @port: The UART port 220 * @uart: The UART port 383 * @data: Pointer to UART port 457 * @port: The UART port 478 * @port: The UART port 521 * @port: The UART port 546 * @port: The UART port 561 * port: The UART port 574 * @port: The UART port 591 * @port: The UART port 853 dev_err(dev, "Failed to add UART: %d\n", err); men_z135_probe() 900 pr_err("Failed to register UART: %d\n", err); men_z135_init() 929 MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
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H A D | tilegx.c | 14 * TILEGx UART driver. 45 /* UART port. */ 51 /* UART access mutex. */ 63 * Read UART rx fifo, and insert the chars into tty buffer. 94 /* First read UART rx fifo. */ handle_receive() 114 * Push one char to UART Write FIFO. 130 * Send chars to UART Write FIFO; called by interrupt handler. 173 * UART Interrupt handler. 345 /* Initialize UART device. */ tilegx_startup() 371 /* Enable UART Tx/Rx Interrupt. */ tilegx_startup() 416 /* Disable UART Tx/Rx Interrupt. */ tilegx_shutdown()
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H A D | arc_uart.c | 2 * ARC On-Chip(fpga) UART Driver 20 * -New Serial Core based ARC UART driver 44 * ARC UART Hardware Specs 49 * UART Register set (this is not a Standards Compliant IP) 61 /* Bits for UART Status Reg (R/W) */ 209 * UART has 4 deep RX-FIFO. Driver's recongnition of this fact arc_serial_rx_chars() 256 * to keep things simple as well as efficient, it writes to UART in polled 289 * notifications from the UART Controller. arc_serial_isr() 337 /* ARC UART doesn't support sending Break signal */ arc_serial_break_ctl() 342 /* Before we hook up the ISR, Disable all UART Interrupts */ arc_serial_startup() 346 dev_warn(port->dev, "Unable to attach ARC UART intr\n"); arc_serial_startup() 373 * Formula for ARC UART is: hw-val = ((CLK/(BAUD*4)) -1) arc_serial_set_termios() 392 * UART doesn't support Parity/Hardware Flow Control; arc_serial_set_termios() 617 /* No point of dev_err since UART itself is hosed here */ arc_serial_probe()
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H A D | altera_jtaguart.c | 2 * altera_jtaguart.c -- Altera JTAG UART driver 4 * Based on mcf.c -- Freescale ColdFire UART driver 33 * Altera JTAG UART register definitions according to the Altera JTAG UART 223 pr_err(DRV_NAME ": unable to attach Altera JTAG UART %d " altera_jtaguart_startup() 258 return (port->type == PORT_ALTERA_JTAGUART) ? "Altera JTAG UART" : NULL; altera_jtaguart_type() 505 MODULE_DESCRIPTION("Altera JTAG UART driver");
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H A D | altera_uart.c | 2 * altera_uart.c -- Altera UART driver 4 * Based on mcf.c -- Freescale ColdFire UART driver 36 * Altera UART register definitions according to the Nios UART datasheet: 325 pr_err(DRV_NAME ": unable to attach Altera UART %d " altera_uart_startup() 362 return (port->type == PORT_ALTERA_UART) ? "Altera UART" : NULL; altera_uart_type() 499 * Define the altera_uart UART driver structure. 653 MODULE_DESCRIPTION("Altera UART driver");
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H A D | bfin_sport_uart.h | 2 * Blackfin On-Chip Sport Emulated UART Driver 14 * This application note describe how to implement a UART on a Sharc DSP,
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H A D | bfin_uart.c | 44 /* UART name and device definitions */ 55 # error KGDB only support UART in PIO mode. 327 * 05000215 - we always clear ETBEI within last UART TX bfin_serial_tx_chars() 515 * 05000215 - we always clear ETBEI within last UART TX bfin_serial_dma_tx_int() 600 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); bfin_serial_startup() 605 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); bfin_serial_startup() 643 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); bfin_serial_startup() 650 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); bfin_serial_startup() 659 * controllers with SPORT2 and SPORT3. UART rx and tx bfin_serial_startup() 682 printk(KERN_NOTICE"Fail to attach UART interrupt\n"); bfin_serial_startup() 689 printk(KERN_NOTICE "Fail to attach UART interrupt\n"); bfin_serial_startup() 710 pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n"); bfin_serial_startup() 726 dev_info(port->dev, "Unable to attach BlackFin UART Modem Status interrupt.\n"); bfin_serial_startup() 874 /* Disable UART */ bfin_serial_set_termios() 890 /* Enable UART */ bfin_serial_set_termios() 904 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; bfin_serial_type()
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H A D | timbuart.h | 20 * Timberdale FPGA UART
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H A D | ar933x_uart.c | 2 * Atheros AR933X SoC built-in UART driver 274 /* disable the UART */ ar933x_uart_set_termios() 297 /* reenable the UART */ ar933x_uart_set_termios() 456 return (port->type == PORT_AR933X) ? "AR933X UART" : NULL; ar933x_uart_type() 668 dev_err(&pdev->dev, "unable to get UART clock\n"); ar933x_uart_probe() 783 MODULE_DESCRIPTION("Atheros AR933X UART driver");
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H A D | serial_ks8695.c | 45 * Access macros for the KS8695 UART 339 retval = request_irq(KS8695_IRQ_UART_TX, ks8695uart_tx_chars, 0, "UART TX", port); ks8695uart_startup() 343 retval = request_irq(KS8695_IRQ_UART_RX, ks8695uart_rx_chars, 0, "UART RX", port); ks8695uart_startup() 347 retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, 0, "UART LineStatus", port); ks8695uart_startup() 351 retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, 0, "UART ModemStatus", port); ks8695uart_startup() 677 printk(KERN_INFO "Serial: Micrel KS8695 UART driver\n"); ks8695uart_init()
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H A D | sirfsoc_uart.h | 289 /* UART FIFO Register */ 330 /* USP-UART Common */ 449 /* UART Port Mask */
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H A D | xilinx_uartps.c | 2 * Cadence UART driver (found in Xilinx Zynq) 52 /* Register offsets for the UART. */ 159 * @port: Pointer to the UART port 280 /* Break if no more data available in the UART buffer */ cdns_uart_isr() 284 /* Get the data from the UART circular buffer cdns_uart_isr() 294 /* Adjust the tail of the UART buffer and wrap cdns_uart_isr() 318 * @clk: UART module input clock 527 /* Break if no more data available in the UART buffer */ cdns_uart_start_tx() 531 /* Get the data from the UART circular buffer and cdns_uart_start_tx() 538 /* Adjust the tail of the UART buffer and wrap cdns_uart_start_tx() 834 * cdns_uart_type - Set UART type to cdns_uart port 892 * cdns_uart_release_port - Release UART port 906 * cdns_uart_config_port - Configure UART port 1513 MODULE_DESCRIPTION("Driver for Cadence UART");
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H A D | sunsu.c | 14 * Converted to new 2.5.x UART layer. 54 * in a UART clock of 1.8462 MHz. 68 * Here we define the default xmit fifo size used for each type of UART. 626 /* Wake up and initialize UART */ sunsu_startup() 632 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ sunsu_startup() 667 * if it is, then bail out, because there's likely no UART sunsu_startup() 689 * Now, initialize the UART sunsu_startup() 938 * splitting all the OBP probing crap from the UART probing. sunsu_config_port() 1082 * Check to see if a UART is really there. Certain broken sunsu_autoconfig() 1117 /* Check for Startech UART's */ sunsu_autoconfig() 1135 * If this is a 16750, and not a cheap UART sunsu_autoconfig() 1170 * Reset the UART. sunsu_autoconfig()
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/linux-4.1.27/sound/oss/ |
H A D | uart401.c | 4 * MPU-401 UART driver (formerly uart401_midi.c) 96 printk(KERN_WARNING "Too much work in interrupt on uart401 (0x%X). UART jabbering ??\n", devc->base); uart401_input_loop() 126 /* Flush the UART */ uart401_open() 205 #define MIDI_SYNTH_NAME "MPU-401 UART" 212 .info = {"MPU-401 (UART) MIDI", 0, 0, SNDCARD_MPU401}, 291 char *name = "MPU-401 (UART) MIDI"; probe_uart401() 300 if (!request_region(hw_config->io_base, 4, "MPU-401 UART")) { probe_uart401() 338 if (request_irq(devc->irq, uart401intr, 0, "MPU-401 UART", devc) < 0) { probe_uart401() 444 printk(KERN_INFO "MPU-401 UART driver Copyright (C) Hannu Savolainen 1993-1997"); init_uart401()
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H A D | uart6850.c | 115 * It looks like there is no input interrupts in the UART mode. Let's try 228 #define MIDI_SYNTH_NAME "6850 UART Midi" 235 .info = {"6850 UART", 0, 0, SNDCARD_UART6850},
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/linux-4.1.27/arch/mips/alchemy/ |
H A D | board-xxs1500.c | 89 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ board_setup() 94 /* Enable UART */ board_setup()
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/linux-4.1.27/arch/mips/mti-sead3/ |
H A D | sead3-platform.c | 20 #define UART(base) \ macro 31 UART(0x1f000900), /* ttyS0 = USB */ 32 UART(0x1f000800), /* ttyS1 = RS232 */
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/linux-4.1.27/arch/arm/mach-tegra/ |
H A D | tegra.c | 66 /* Debug UART initialization required */ 68 /* Debug UART physical address */ 70 /* Debug UART virtual address */
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/linux-4.1.27/drivers/tty/serial/jsm/ |
H A D | jsm_neo.c | 22 #include <linux/serial_reg.h> /* For the various UART offsets */ 62 /* Turn on UART enhanced bits */ neo_set_cts_flow_control() 68 /* Feed the UART our trigger levels */ neo_set_cts_flow_control() 94 /* Turn on UART enhanced bits */ neo_set_rts_flow_control() 106 * From the Neo UART spec sheet: neo_set_rts_flow_control() 133 /* Turn on UART enhanced bits */ neo_set_ixon_flow_control() 142 /* Tell UART what start/stop chars it should be looking for */ neo_set_ixon_flow_control() 171 /* Turn on UART enhanced bits */ neo_set_ixoff_flow_control() 180 /* Tell UART what start/stop chars it should be looking for */ neo_set_ixoff_flow_control() 212 /* Turn on UART enhanced bits */ neo_set_no_input_flow_control() 250 /* Turn on UART enhanced bits */ neo_set_no_output_flow_control() 276 /* Tell UART what start/stop chars it should be looking for */ neo_set_new_start_stop_chars() 310 * If the UART is not in FIFO mode, force the FIFO copy to neo_copy_data_from_uart_to_queue() 313 * On the other hand, if the UART IS in FIFO mode, then ask neo_copy_data_from_uart_to_queue() 314 * the UART to give us an approximation of data it has RX'ed. neo_copy_data_from_uart_to_queue() 400 * Now cleanup any leftover bytes still in the UART. neo_copy_data_from_uart_to_queue() 501 /* No data to write to the UART */ neo_copy_data_from_queue_to_uart() 505 /* If port is "stopped", don't send any data to the UART */ neo_copy_data_from_queue_to_uart() 616 /* Make the UART raise any of the output signals we want up */ neo_assert_modem_signals() 645 /* Check to see if the UART feels it completely flushed the FIFO. */ neo_flush_uart_write() 649 "Still flushing TX UART... i: %d\n", i); neo_flush_uart_write() 677 /* Check to see if the UART feels it completely flushed the FIFO. */ neo_flush_uart_read() 681 "Still flushing RX UART... i: %d\n", i); neo_flush_uart_read() 762 /* Transfer data (if any) from Write Queue -> UART. */ neo_parse_isr() 777 * Since the UART detected either an XON or neo_parse_isr() 918 /* Transfer data (if any) from Write Queue -> UART. */ neo_parse_lsr() 926 /* Transfer data (if any) from Write Queue -> UART. */ neo_parse_lsr() 933 * Send any/all changes to the line to the UART. 1205 * TXRDY interrupt clears after reading ISR register for the UART channel. neo_intr() 1228 * The UART triggered us with a bogus interrupt type. neo_intr() 1314 /* Clear out UART and FIFO */ neo_uart_init() 1327 * Make the UART completely turn off. 1331 /* Turn off UART enhanced bits */ neo_uart_off() 1366 /* Tell the UART to start sending the break */ neo_send_break() 1380 * Sends a specific character as soon as possible to the UART,
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H A D | jsm_cls.c | 30 #include <linux/serial_reg.h> /* For the various UART offsets */ 350 /* Make the UART raise any of the output signals we want up */ cls_assert_modem_signals() 471 /* No data to write to the UART */ cls_copy_data_from_queue_to_uart() 475 /* If port is "stopped", don't send any data to the UART */ cls_copy_data_from_queue_to_uart() 597 /* Transfer data (if any) from Write Queue -> UART. */ cls_parse_isr() 628 /* Check to see if the UART feels it completely flushed FIFO */ cls_flush_uart_write() 632 "Still flushing TX UART... i: %d\n", i); cls_flush_uart_write() 649 * read FIFO in the UART here. cls_flush_uart_read() 655 * Presumably, this is a bug in this UART. cls_flush_uart_read() 685 * Send any/all changes to the line to the UART. 867 /* Inits UART */ cls_uart_init() 891 /* Clear out UART and FIFO */ cls_uart_init() 905 * Turns off UART. 937 * Starts sending a break thru the UART. 943 /* Tell the UART to start sending the break */ cls_send_break() 954 * Sends a specific character as soon as possible to the UART,
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H A D | jsm.h | 160 u32 bd_uart_offset; /* Space between each UART */ 224 /* Pointers to the "mapped" UART structs */ 260 * Per channel/port Classic UART structures * 315 * Per channel/port NEO UART structure * 395 * back to us from the UART's 32bit interrupt register 402 #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
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H A D | jsm_tty.c | 259 /* Tell UART to init itself */ jsm_tty_open() 303 /* Turn off UART interrupts for this port */ jsm_tty_close() 617 * UART errors, we will have to walk each character jsm_input() 776 * 1) HWFLOW (RTS) - Turn off the UART's Receive interrupt. jsm_check_queue_flow_control() 777 * This will cause the UART's FIFO to back up, and force jsm_check_queue_flow_control() 814 * 1) HWFLOW (RTS) - Turn back on the UART's Receive interrupt. jsm_check_queue_flow_control() 815 * This will cause the UART's FIFO to raise RTS back up, jsm_check_queue_flow_control()
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/linux-4.1.27/arch/mips/include/asm/mach-cobalt/ |
H A D | irq.h | 36 * 5 - 16550 UART
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/linux-4.1.27/arch/mn10300/include/asm/ |
H A D | serial.h | 1 /* Standard UART definitions
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/linux-4.1.27/arch/arm/mach-s3c64xx/ |
H A D | dev-uart.c | 8 * Base S3C64XX UART resource and device definitions
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/linux-4.1.27/arch/arm/mach-w90x900/include/mach/ |
H A D | uncompress.h | 21 /* Defines for UART registers */
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/linux-4.1.27/arch/arm/mach-imx/ |
H A D | mach-kzm_arm11_01.c | 62 * External UART for touch panel on FPGA 68 * KZM-ARM11-01 has an external UART on FPGA 112 * GPIO 1-1: external UART interrupt line kzm_init_ext_uart() 119 * Unmask UART interrupt kzm_init_ext_uart()
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/linux-4.1.27/include/linux/dma/ |
H A D | hsu.h | 2 * Driver for the High Speed UART DMA
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/linux-4.1.27/sound/drivers/mpu401/ |
H A D | mpu401_uart.c | 3 * Routines for control of MPU-401 in UART mode 5 * MPU-401 supports UART mode which is not capable generate transmit 43 MODULE_DESCRIPTION("Routines for control of MPU-401 in UART mode"); 127 * snd_mpu401_uart_interrupt - generic MPU401-UART interrupt handler 131 * Processes the interrupt for MPU401-UART i/o. 148 * snd_mpu401_uart_interrupt_tx - generic MPU401-UART transmit irq handler 152 * Processes the interrupt for MPU401-UART output. 221 * send a UART command 508 * snd_mpu401_uart_new - create an MPU401-UART instance 561 mpu->res = request_region(port, res_size, "MPU401 UART"); snd_mpu401_uart_new() 584 "MPU401 UART", (void *) mpu)) { snd_mpu401_uart_new()
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H A D | mpu401.c | 2 * Driver for generic MPU-401 boards (UART mode only) 33 MODULE_DESCRIPTION("MPU-401 UART"); 81 strcpy(card->driver, "MPU-401 UART"); snd_mpu401_create()
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/linux-4.1.27/drivers/misc/ibmasm/ |
H A D | uart.c | 41 /* read the uart scratch register to determine if the UART ibmasm_register_uart() 45 dev_info(sp->dev, "IBM SP UART not registered, owned by service processor\n"); ibmasm_register_uart()
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/linux-4.1.27/drivers/dma/hsu/ |
H A D | pci.c | 2 * PCI driver for the High Speed UART DMA 123 MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
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H A D | hsu.c | 2 * Core driver for the High Speed UART DMA 16 * 1. Even number chans are used for DMA Read (UART TX), odd chans for DMA 17 * Write (UART RX). 497 MODULE_DESCRIPTION("High Speed UART DMA core driver");
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H A D | hsu.h | 2 * Driver for the High Speed UART DMA
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/linux-4.1.27/arch/mips/loongson/loongson-3/ |
H A D | irq.c | 56 /* Workaround: UART IRQ may deliver to any core */ mask_loongson_irq() 73 /* Workaround: UART IRQ may deliver to any core */ unmask_loongson_irq()
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/linux-4.1.27/arch/arm/mach-ks8695/include/mach/ |
H A D | regs-uart.h | 7 * KS8695 - UART register and bit definitions. 23 * UART registers
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H A D | regs-irq.h | 32 #define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */
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/linux-4.1.27/drivers/usb/serial/ |
H A D | mct_u232.h | 161 * 16450 or 16550 UART. The FreeBSD handbook (appendix F.4 "Input/Output 210 * between the last bit of the data and the Stop Bit. The UART will also 244 * Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver 246 * addition, the UART modem control outputs are connected to the UART 252 * 8250/16450/16550 UART. 255 * Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS 257 * Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART 275 * UART. 276 * Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART. 277 * Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART. 278 * Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART. 300 * Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero. 457 * embedded UART. Exhaustive documentation for these is available at:
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H A D | ti_usb_3410_5052.h | 245 /* UART addresses */ 246 #define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */ 247 #define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */ 248 #define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */ 249 #define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */
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H A D | io_ti.h | 25 /* UART Defines */ 28 #define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */ 156 /* UART settings */
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H A D | io_ionsp.h | 145 // cccc: 00-07 2-byte commands. Write UART register 0-7 with 147 // UART register numbers and contents. 178 #define IOSP_CMD_OPEN_PORT 0x00 // Enable ints, init UART. (NO PARAM) 234 // Tells Edgeport how it can stop incoming UART data 255 // Tells Edgeport what signal(s) will stop it from transmitting UART data 282 // the last Tx char leaves the UART. 345 // ssss: 00-07 2-byte status. ssss identifies which UART register 378 // UART when the LSR error occurred
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/linux-4.1.27/drivers/misc/ |
H A D | fsa9480.c | 87 * 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO 160 } else if (!strncmp(buf, "UART", 4)) { fsa9480_set_switch() 193 return sprintf(buf, "UART\n"); fsa9480_get_switch() 222 /* UART */ fsa9480_show_device() 224 return sprintf(buf, "UART\n"); fsa9480_show_device() 295 /* UART */ fsa9480_detect_dev() 325 /* UART */ fsa9480_detect_dev()
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/linux-4.1.27/drivers/staging/dgnc/ |
H A D | dgnc_neo.c | 23 #include <linux/serial_reg.h> /* For the various UART offsets */ 119 /* Turn on UART enhanced bits */ neo_set_cts_flow_control() 125 /* Feed the UART our trigger levels */ neo_set_cts_flow_control() 155 /* Turn on UART enhanced bits */ neo_set_rts_flow_control() 167 * From the Neo UART spec sheet: neo_set_rts_flow_control() 193 /* Turn on UART enhanced bits */ neo_set_ixon_flow_control() 202 /* Tell UART what start/stop chars it should be looking for */ neo_set_ixon_flow_control() 231 /* Turn on UART enhanced bits */ neo_set_ixoff_flow_control() 240 /* Tell UART what start/stop chars it should be looking for */ neo_set_ixoff_flow_control() 273 /* Turn on UART enhanced bits */ neo_set_no_input_flow_control() 311 /* Turn on UART enhanced bits */ neo_set_no_output_flow_control() 339 /* Tell UART what start/stop chars it should be looking for */ neo_set_new_start_stop_chars() 430 /* Transfer data (if any) from Write Queue -> UART. */ neo_parse_isr() 441 * Since the UART detected either an XON or neo_parse_isr() 576 /* Transfer data (if any) from Write Queue -> UART. */ neo_parse_lsr() 585 /* Transfer data (if any) from Write Queue -> UART. */ neo_parse_lsr() 593 * Send any/all changes to the line to the UART. 784 * Have the UART interrupt on modem signal changes ONLY when neo_param() 1028 * TXRDY interrupt clears after reading ISR register for the UART channel. neo_intr() 1051 * The UART triggered us with a bogus interrupt type. neo_intr() 1131 * If the UART is not in FIFO mode, force the FIFO copy to neo_copy_data_from_uart_to_queue() 1134 * On the other hand, if the UART IS in FIFO mode, then ask neo_copy_data_from_uart_to_queue() 1135 * the UART to give us an approximation of data it has RX'ed. neo_copy_data_from_uart_to_queue() 1227 * Now cleanup any leftover bytes still in the UART. neo_copy_data_from_uart_to_queue() 1367 /* Check to see if the UART feels it completely flushed the FIFO. */ neo_flush_uart_write() 1397 /* Check to see if the UART feels it completely flushed the FIFO. */ neo_flush_uart_read() 1422 /* No data to write to the UART */ neo_copy_data_from_queue_to_uart() 1426 /* If port is "stopped", don't send any data to the UART */ neo_copy_data_from_queue_to_uart() 1612 /* Make the UART raise any of the output signals we want up */ neo_assert_modem_signals() 1628 /* Give time for the UART to actually raise/drop the signals */ neo_assert_modem_signals() 1672 /* Clear out UART and FIFO */ neo_uart_init() 1687 * Make the UART completely turn off. 1691 /* Turn off UART enhanced bits */ neo_uart_off() 1747 /* Tell the UART to start sending the break */ neo_send_break() 1761 * Sends a specific character as soon as possible to the UART,
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H A D | dgnc_neo.h | 22 * Per channel/port NEO UART structure * 117 * back to us from the UART's 32bit interrupt register 124 #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
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H A D | dgnc_cls.c | 22 #include <linux/serial_reg.h> /* For the various UART offsets */ 405 /* Transfer data (if any) from Write Queue -> UART. */ cls_parse_isr() 431 * Send any/all changes to the line to the UART. 627 * Have the UART interrupt on modem signal changes ONLY when cls_param() 964 * read FIFO in the UART here. cls_flush_uart_read() 970 * Presumably, this is a bug in this UART. cls_flush_uart_read() 990 /* No data to write to the UART */ cls_copy_data_from_queue_to_uart() 994 /* If port is "stopped", don't send any data to the UART */ cls_copy_data_from_queue_to_uart() 1118 /* Make the UART raise any of the output signals we want up */ cls_assert_modem_signals() 1133 /* Give time for the UART to actually drop the signals */ cls_assert_modem_signals() 1159 /* Inits UART */ cls_uart_init() 1183 /* Clear out UART and FIFO */ cls_uart_init() 1197 * Turns off UART. 1235 * Starts sending a break thru the UART. 1266 /* Tell the UART to start sending the break */ cls_send_break() 1277 * Sends a specific character as soon as possible to the UART,
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H A D | dgnc_cls.h | 20 * Per channel/port Classic UART structure *
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/linux-4.1.27/arch/x86/platform/ce4100/ |
H A D | ce4100.c | 54 * The UART Tx interrupts are not set under some conditions and therefore serial 73 /* see if the UART's XMIT interrupt is enabled */ ce4100_mem_serial_in() 76 /* now check to see if the UART should be ce4100_mem_serial_in()
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/linux-4.1.27/arch/arm/mach-pxa/ |
H A D | colibri-pxa320.c | 48 /* UART 1 configuration (may be set by bootloader) */ 58 /* UART 2 configuration */ 64 /* UART 3 configuration */
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H A D | capc7117.c | 75 /* TI16C752 UART support */
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/linux-4.1.27/arch/arm/mach-nomadik/ |
H A D | cpu-8815.c | 71 #define NOMADIK_UART2_BASE 0x101F2000 /* UART 2 interface */ 80 #define NOMADIK_UART1_BASE 0x101FB000 /* UART 1 interface */ 82 #define NOMADIK_UART0_BASE 0x101FD000 /* UART 0 interface */
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/linux-4.1.27/arch/arm/mach-versatile/include/mach/ |
H A D | platform.h | 176 * - used to acknowledge and control MMCI and UART interrupts 196 #define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */ 330 #define INT_UARTINT0 12 /* UART 0 on development chip */ 331 #define INT_UARTINT1 13 /* UART 1 on development chip */ 332 #define INT_UARTINT2 14 /* UART 2 on development chip */ 367 #define SIC_INT_UART3 6 /* UART 3 empty or data available */
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/linux-4.1.27/drivers/bluetooth/ |
H A D | hci_uart.h | 3 * Bluetooth HCI UART driver 37 /* UART protocols */
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H A D | btuart_cs.c | 3 * Driver for Bluetooth PCMCIA cards with HCI UART interface 57 MODULE_DESCRIPTION("Bluetooth driver for Bluetooth PCMCIA cards with HCI UART interface"); 493 /* Reset UART */ btuart_open() 499 /* Initialize UART */ btuart_open() 538 /* Reset UART */ btuart_close()
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H A D | hci_ldisc.c | 3 * Bluetooth HCI UART driver 65 BT_INFO("HCI UART protocol %s registered", p->name); hci_uart_register_proto() 209 /* Nothing to do for UART driver */ hci_uart_open() 646 BT_INFO("HCI UART driver ver %s", VERSION); hci_uart_init() 724 MODULE_DESCRIPTION("Bluetooth HCI UART driver ver " VERSION);
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/linux-4.1.27/arch/powerpc/platforms/85xx/ |
H A D | twr_p102x.c | 105 /* On P1025TWR board, the UCC7 acted as UART port. twr_p1025_setup_arch() 109 * The UCC7 UART just can use RXD and TXD pins. twr_p1025_setup_arch()
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/linux-4.1.27/arch/xtensa/platforms/xtfpga/include/platform/ |
H A D | hardware.h | 41 /* UART */
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/linux-4.1.27/arch/mips/bcm47xx/ |
H A D | serial.c | 96 MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms");
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/linux-4.1.27/arch/mips/include/asm/mach-ath79/ |
H A D | ar933x_uart.h | 2 * Atheros AR933X UART defines
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/linux-4.1.27/arch/mips/include/asm/mach-rc32434/ |
H A D | gpio.h | 50 /* UART GPIO signals */
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/linux-4.1.27/arch/arm/mach-integrator/ |
H A D | integrator_ap.c | 77 * f1600000 16000000 UART 0 78 * f1700000 17000000 UART 1 210 * For the PL010 found in the Integrator/AP some of the UART control is 258 /* For the Device Tree, add in the UART callbacks as AUXDATA */
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H A D | integrator_cp.c | 59 * f1600000 16000000 UART 0 60 * f1700000 17000000 UART 1 243 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
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/linux-4.1.27/arch/arm/mach-lpc32xx/include/mach/ |
H A D | uncompress.h | 28 * Uncompress output is hardcoded to standard UART 5
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/linux-4.1.27/include/linux/mfd/ |
H A D | max77693.h | 53 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
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/linux-4.1.27/include/linux/mmc/ |
H A D | sdio_ids.h | 13 #define SDIO_CLASS_UART 0x01 /* standard UART interface */
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/linux-4.1.27/drivers/net/irda/ |
H A D | sh_sir.c | 40 #define IRIF_UART_STS2 0x002E /* UART status 2 */ 41 #define IRIF_UART0 0x0030 /* UART control */ 42 #define IRIF_UART1 0x0032 /* UART status */ 43 #define IRIF_UART2 0x0034 /* UART mode */ 44 #define IRIF_UART3 0x0036 /* UART transmit data */ 45 #define IRIF_UART4 0x0038 /* UART receive data */ 46 #define IRIF_UART5 0x003A /* UART interrupt mask */ 47 #define IRIF_UART6 0x003C /* UART baud rate error correction */ 48 #define IRIF_UART7 0x003E /* UART baud rate count set */ 359 dev_warn(dev, "UART freq error margin over %d\n", tmp); sh_sir_set_baudrate()
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H A D | vlsi_ir.h | 49 VLSI_PCI_IRMISC = 0x42 /* mainly legacy UART related */ 133 /* legacy UART emulation - not used by this driver - would require: 136 * - IRMISC_UARTEN must be set to enable UART address decoding 152 /* legacy UART control */ 154 IRMISC_UARTTST = 0x80, /* UART test mode - "always write 0" */ 155 IRMISC_UARTEN = 0x04, /* enable UART address decoding */ 157 /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */ 181 /* 0x0a-0x0f: reserved / duplicated UART regs */ 189 /* 0x1e-0x1f: reserved / duplicated UART regs */ 203 * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-) 213 IRINTR_OE_EN = 0x02, /* UART rx fifo overrun error interrupt enable */ 214 IRINTR_OE_INT = 0x01 /* UART rx fifo overrun error (read LSR to clear) */ 303 * when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode 500 * I see would be using the legacy UART emulation in SIR mode.
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/linux-4.1.27/drivers/char/mwave/ |
H A D | 3780i.h | 85 #define DSP_UartCfg1Index 0x0003 /* UART config register 1 */ 86 #define DSP_UartCfg2Index 0x0004 /* UART config register 2 */ 182 unsigned short Uart:1; /* RW: Reset UART interface */ 261 * the only values maintained by the 3780i support layer are the saved UART 307 /* Saved UART registers. These are maintained by the 3780i support layer. */ 308 int bUartSaved; /* True after a successful save of the UART registers */
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/linux-4.1.27/drivers/staging/speakup/ |
H A D | serialio.c | 64 /* Disable UART interrupts, set DTR and RTS high spk_serial_init() 75 /* If we read 0xff from the LSR, there is no UART here. */ spk_serial_init()
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/linux-4.1.27/arch/unicore32/kernel/ |
H A D | puv3-core.c | 270 platform_device_register_simple("PKUnity-v3-UART", 0, puv3_core_init() 272 platform_device_register_simple("PKUnity-v3-UART", 1, puv3_core_init()
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/linux-4.1.27/arch/microblaze/kernel/ |
H A D | early_printk.c | 34 * we'll never timeout on a working UART. early_printk_uartlite_putc() 75 * we'll never timeout on a working UART. early_printk_uart16550_putc()
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H A D | misc.S | 75 * Load a TLB entry for the UART, so that microblaze_progress() can use
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/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/ |
H A D | msp_cic_int.h | 100 /* UART 0 */ 132 /* UART 1 */
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H A D | msp_slp_int.h | 99 /* UART 0 */ 122 /* UART 1 */
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/linux-4.1.27/arch/sh/include/asm/ |
H A D | smc37c93x.h | 53 /* UART stuff. Only for debugging. */ 54 /* UART Register */
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/linux-4.1.27/arch/powerpc/boot/ |
H A D | cuboot-acadia.c | 41 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ 42 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
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/linux-4.1.27/arch/powerpc/include/asm/ |
H A D | cpm1.h | 73 /* Define enough so I can at least use the serial port as a UART. 166 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 167 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 391 /* SCC as UART 404 ushort scc_uaddr1; /* UART address character 1 */ 405 ushort scc_uaddr2; /* UART address character 2 */ 421 /* SCC Event and Mask registers when it is used as a UART. 435 /* The SCC PMSR when used as a UART.
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/linux-4.1.27/arch/blackfin/kernel/ |
H A D | early_printk.c | 206 * the UART now (but only if we are running on the processor we think early_trap_c() 208 * and cause other problems. Nothing comes out the UART, but it does early_trap_c()
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/linux-4.1.27/arch/arm/mach-mmp/ |
H A D | pxa910.c | 124 * UART1 - Slow UART (can be used both by AP and CP) 125 * UART2/3 - Fast UART
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/linux-4.1.27/sound/isa/msnd/ |
H A D | msnd_midi.c | 4 * Routines for control of MPU-401 in UART mode 6 * MPU-401 supports UART mode which is not capable generate transmit
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/linux-4.1.27/drivers/staging/rtl8712/ |
H A D | rtl8712_gp_bitdef.h | 68 #define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/
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/linux-4.1.27/arch/mips/include/asm/mach-ath25/ |
H A D | ath25_platform.h | 28 #define BD_EXTUARTCLK 0x00000040 /* External UART clock */
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/linux-4.1.27/arch/mips/lasat/ |
H A D | serial.c | 2 * Registration of Lasat UART platform device.
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/linux-4.1.27/arch/mips/loongson/lemote-2f/ |
H A D | irq.c | 83 } else if (pending & CAUSEF_IP3) /* CPU UART */ mach_irq_dispatch()
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/linux-4.1.27/arch/mn10300/unit-asb2305/include/unit/ |
H A D | serial.h | 24 * The ASB2305 has an 18.432 MHz clock the UART
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/linux-4.1.27/arch/arm/plat-samsung/ |
H A D | pm-debug.c | 80 S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", s3c_pm_save_uarts()
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/linux-4.1.27/arch/arm/include/asm/hardware/ |
H A D | it8152.h | 54 IT8152_LD_IRQ(5) UART
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/linux-4.1.27/arch/arm/mach-davinci/ |
H A D | serial.c | 84 pr_err("%s:%d: failed to get UART%d clock\n", davinci_serial_init()
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/linux-4.1.27/arch/x86/kernel/ |
H A D | early_printk.c | 213 * location of a PCI device that must be a UART device. 259 * Verify it is a UART type device early_pci_serial_init() 292 /* Sometimes, we want to leave the UART alone early_pci_serial_init()
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/linux-4.1.27/include/linux/amba/ |
H A D | serial.h | 29 * From AMBA UART (PL010) Block Specification 31 * UART Register Offsets. 105 #define UART01x_CR_UARTEN 0x0001 /* UART enable */
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/linux-4.1.27/sound/isa/wavefront/ |
H A D | wavefront_midi.c | 11 * Note that there is also an MPU-401 emulation (actually, a UART-401 15 * The interface is essentially just a UART-401, but is has the 28 * something other than 0 and 1 if the CS4232 UART/MPU-401 interface 495 until its set into UART mode. snd_wavefront_midi_start() 525 snd_printk ("cannot set UART mode for MIDI interface"); snd_wavefront_midi_start()
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/linux-4.1.27/drivers/clk/tegra/ |
H A D | clk-tegra-periph.c | 179 #define UART(_name, _parents, _offset,\ macro 500 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), 501 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), 502 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), 503 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), 504 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
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/linux-4.1.27/drivers/acpi/acpica/ |
H A D | utresrc.c | 198 "UART" 243 /* UART serial bus endian */ 250 /* UART serial bus bits per byte */ 263 /* UART serial bus stop bits */ 272 /* UART serial bus flow control */ 281 /* UART serial bus parity type */
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/linux-4.1.27/sound/pci/emu10k1/ |
H A D | emumpu401.c | 3 * Routines for control of EMU10K1 MPU-401 in UART mode 360 if ((err = emu10k1_midi_init(emu, midi, 0, "EMU10K1 MPU-401 (UART)")) < 0) snd_emu10k1_midi() 378 if ((err = emu10k1_midi_init(emu, midi, 0, "Audigy MPU-401 (UART)")) < 0) snd_emu10k1_audigy_midi()
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