Searched refs:TIMER_CR (Results 1 - 2 of 2) sorted by relevance
| /linux-4.1.27/arch/arm/mach-gemini/ |
| H A D | time.c | 26 #define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30) macro
45 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_next_event()
50 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_next_event()
57 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_next_event()
75 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_mode()
78 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_mode()
88 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_mode()
91 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_set_mode()
161 writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); gemini_timer_init()
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| /linux-4.1.27/drivers/clocksource/ |
| H A D | moxart_timer.c | 34 #define TIMER_CR 0x30 macro
39 * TIMER_CR flags:
67 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_clkevt_mode()
72 writel(TIMER1_ENABLE, base + TIMER_CR); moxart_clkevt_mode()
77 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_clkevt_mode()
87 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_clkevt_next_event()
92 writel(TIMER1_ENABLE, base + TIMER_CR); moxart_clkevt_next_event()
151 writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); moxart_timer_init()
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