Searched refs:TEGRA30_CLK_PLL_M_OUT1 (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_M_OUT1 178 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_M_OUT1 178 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_M_OUT1 178 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_M_OUT1 178 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_M_OUT1 178 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_M_OUT1 178 macro
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-tegra30.c599 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
954 clks[TEGRA30_CLK_PLL_M_OUT1] = clk; tegra30_pll_init()

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