Searched refs:TEGRA20_CLK_UARTE (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h87 #define TEGRA20_CLK_UARTE 66 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h87 #define TEGRA20_CLK_UARTE 66 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h87 #define TEGRA20_CLK_UARTE 66 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h87 #define TEGRA20_CLK_UARTE 66 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h87 #define TEGRA20_CLK_UARTE 66 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dtegra20-car.h87 #define TEGRA20_CLK_UARTE 66 macro
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-tegra20.c523 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
797 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
1046 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},

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