Searched refs:TEGRA20_CLK_PLL_P_OUT1 (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h144 #define TEGRA20_CLK_PLL_P_OUT1 122 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h144 #define TEGRA20_CLK_PLL_P_OUT1 122 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h144 #define TEGRA20_CLK_PLL_P_OUT1 122 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h144 #define TEGRA20_CLK_PLL_P_OUT1 122 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dtegra20-car.h144 #define TEGRA20_CLK_PLL_P_OUT1 122 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dtegra20-car.h144 #define TEGRA20_CLK_PLL_P_OUT1 122 macro
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-tegra20.c434 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
556 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
1030 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},

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