Searched refs:TCLR (Results 1 – 2 of 2) sorted by relevance
| /linux-4.1.27/Documentation/devicetree/bindings/mtd/ |
| D | fsmc-nand.txt | 15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
18 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
|
| /linux-4.1.27/drivers/tty/ |
| D | synclink.c | 368 #define TCLR 0x3a /* Transmit count Limit Register */ macro
5625 usc_OutReg( info, TCLR, (u16)FrameSize ); in usc_start_transmitter()
6115 usc_OutReg( info, TCLR, 2 ); in usc_loopback_frame()
6988 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] ); in mgsl_register_test()
6995 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) || in mgsl_register_test()
7215 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count ); in mgsl_dma_test()
|