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Searched refs:SPORT2_MRCS0 (Results 1 – 4 of 4) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h756 #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ macro
DcdefBF538.h340 #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
341 #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h993 #define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Regis… macro
DcdefBF54x_base.h1703 #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
1704 #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)