Searched refs:SPORT0_MCMC1 (Results 1 - 14 of 14) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h594 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
595 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
H A DdefBF532.h134 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ macro
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF547.h77 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
78 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
H A DdefBF547.h50 #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ macro
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h276 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
277 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
H A DdefBF512.h172 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ macro
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h293 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
294 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
H A DdefBF522.h169 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ macro
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
H A DcdefBF561.h404 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
405 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
H A DdefBF561.h246 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ macro
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF534.h258 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
259 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
H A DdefBF534.h148 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ macro
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h240 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
241 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
H A DdefBF538.h138 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ macro

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