Searched refs:SPI1_IMSK_CLR (Results 1 – 2 of 2) sorted by relevance
1324 #define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */ macro
182 #define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)183 #define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)