Searched refs:SMU7_MAX_LEVELS_LINK (Results 1 – 3 of 3) sorted by relevance
44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. macro
325 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
3380 SMU7_MAX_LEVELS_LINK); in ci_setup_default_pcie_tables()