Searched refs:SET_FIELD (Results 1 - 5 of 5) sorted by relevance
/linux-4.1.27/drivers/net/wireless/rt2x00/ |
H A D | rt2x00reg.h | 246 #define SET_FIELD(__reg, __type, __field, __value)\ macro 263 SET_FIELD(__reg, struct rt2x00_field32, __field, __value) 268 SET_FIELD(__reg, struct rt2x00_field16, __field, __value) 273 SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
|
/linux-4.1.27/drivers/staging/sm750fb/ |
H A D | sm750_help.h | 15 #define SET_FIELD(d,f,v) (((d) & ~GET_MASK(f)) | \ macro
|
/linux-4.1.27/drivers/gpu/drm/gma500/ |
H A D | cdv_intel_display.c | 151 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | cdv_sb_read() 152 SET_FIELD(SB_DEST_DPLL, SB_DEST) | cdv_sb_read() 153 SET_FIELD(0xf, SB_BYTE_ENABLE)); cdv_sb_read() 187 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | cdv_sb_write() 188 SET_FIELD(SB_DEST_DPLL, SB_DEST) | cdv_sb_write() 189 SET_FIELD(0xf, SB_BYTE_ENABLE)); cdv_sb_write() 321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); cdv_dpll_set_clock_cdv() 324 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv() 327 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv() 330 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv() 333 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv()
|
H A D | psb_intel_reg.h | 1292 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) macro
|
/linux-4.1.27/drivers/iommu/ |
H A D | msm_iommu_hw-8xxx.h | 42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v)) 44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v)) 48 #define SET_FIELD(addr, mask, shift, v) \ macro
|
Completed in 207 milliseconds