Searched refs:SET_FIELD (Results 1 - 5 of 5) sorted by relevance

/linux-4.1.27/drivers/net/wireless/rt2x00/
H A Drt2x00reg.h246 #define SET_FIELD(__reg, __type, __field, __value)\ macro
263 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
268 SET_FIELD(__reg, struct rt2x00_field16, __field, __value)
273 SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
/linux-4.1.27/drivers/staging/sm750fb/
H A Dsm750_help.h15 #define SET_FIELD(d,f,v) (((d) & ~GET_MASK(f)) | \ macro
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c151 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | cdv_sb_read()
152 SET_FIELD(SB_DEST_DPLL, SB_DEST) | cdv_sb_read()
153 SET_FIELD(0xf, SB_BYTE_ENABLE)); cdv_sb_read()
187 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | cdv_sb_write()
188 SET_FIELD(SB_DEST_DPLL, SB_DEST) | cdv_sb_write()
189 SET_FIELD(0xf, SB_BYTE_ENABLE)); cdv_sb_write()
321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); cdv_dpll_set_clock_cdv()
324 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv()
327 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv()
330 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv()
333 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); cdv_dpll_set_clock_cdv()
H A Dpsb_intel_reg.h1292 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) macro
/linux-4.1.27/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
48 #define SET_FIELD(addr, mask, shift, v) \ macro

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