Searched refs:SDC3_RESET (Results 1 - 21 of 21) sorted by relevance
| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/reset/ |
| H A D | qcom,gcc-ipq806x.h | 74 #define SDC3_RESET 57 macro
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| H A D | qcom,gcc-msm8660.h | 82 #define SDC3_RESET 65 macro
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| H A D | qcom,gcc-msm8960.h | 77 #define SDC3_RESET 60 macro
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| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/reset/ |
| H A D | qcom,gcc-ipq806x.h | 74 #define SDC3_RESET 57 macro
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| H A D | qcom,gcc-msm8660.h | 82 #define SDC3_RESET 65 macro
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| H A D | qcom,gcc-msm8960.h | 77 #define SDC3_RESET 60 macro
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| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/reset/ |
| H A D | qcom,gcc-ipq806x.h | 74 #define SDC3_RESET 57 macro
|
| H A D | qcom,gcc-msm8660.h | 82 #define SDC3_RESET 65 macro
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| H A D | qcom,gcc-msm8960.h | 77 #define SDC3_RESET 60 macro
|
| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/reset/ |
| H A D | qcom,gcc-ipq806x.h | 74 #define SDC3_RESET 57 macro
|
| H A D | qcom,gcc-msm8660.h | 82 #define SDC3_RESET 65 macro
|
| H A D | qcom,gcc-msm8960.h | 77 #define SDC3_RESET 60 macro
|
| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/reset/ |
| H A D | qcom,gcc-ipq806x.h | 74 #define SDC3_RESET 57 macro
|
| H A D | qcom,gcc-msm8660.h | 82 #define SDC3_RESET 65 macro
|
| H A D | qcom,gcc-msm8960.h | 77 #define SDC3_RESET 60 macro
|
| /linux-4.1.27/include/dt-bindings/reset/ |
| H A D | qcom,gcc-ipq806x.h | 74 #define SDC3_RESET 57 macro
|
| H A D | qcom,gcc-msm8660.h | 82 #define SDC3_RESET 65 macro
|
| H A D | qcom,gcc-msm8960.h | 77 #define SDC3_RESET 60 macro
|
| /linux-4.1.27/drivers/clk/qcom/ |
| H A D | gcc-msm8960.c | 3220 [SDC3_RESET] = { 0x2870 },
3430 [SDC3_RESET] = { 0x2870 },
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| H A D | gcc-ipq806x.c | 2370 [SDC3_RESET] = { 0x2870, 0 },
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| H A D | gcc-msm8660.c | 2646 [SDC3_RESET] = { 0x2870 },
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