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Searched refs:REG_WR_INT_VECT (Results 1 – 67 of 67) sorted by relevance

/linux-4.1.27/arch/cris/arch-v32/kernel/
Dirq.c214 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, in block_irq()
220 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, in block_irq()
238 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, in unblock_irq()
244 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, in unblock_irq()
393 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask); in crisv32_do_multiple()
426 REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask); in crisv32_do_multiple()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
Dmarb_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
318 #ifndef REG_WR_INT_VECT
319 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dstrcop_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dirq_nmi_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dconfig_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Drt_trace_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dmarb_bp_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Data_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dbif_slave_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dbif_core_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dser_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Deth_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dsser_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Ddma_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dextmem_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dbif_dma_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dmarb_bar_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
340 #ifndef REG_WR_INT_VECT
341 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dstrmux_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dl2cache_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dclkgen_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dmarb_foo_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
466 #ifndef REG_WR_INT_VECT
467 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dtimer_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dddr2_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dpinmux_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dpio_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dintr_vect_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dgio_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dmarb_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
318 #ifndef REG_WR_INT_VECT
319 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dstrmux_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dconfig_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dmarb_bp_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dtimer_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dbif_slave_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dintr_vect_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dgio_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dbif_core_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dpinmux_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Dbif_dma_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sap_in_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sap_out_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_spu_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_cpu_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_mpu_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_cfg_defs.h56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_scrc_out_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_scrc_in_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_fifo_in_extra_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_fifo_out_extra_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_trigger_grp_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_mpu_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sap_in_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_crc_par_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_fifo_in_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_timer_grp_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_fifo_out_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_dmc_out_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sap_out_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_dmc_in_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_spu_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_spu_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_cpu_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_mpu_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
Diop_sw_cfg_defs.h59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ macro
/linux-4.1.27/arch/cris/arch-v32/mach-a3/
Darbiter.c218 REG_WR_INT_VECT(marb_foo, regi_marb_foo, in crisv32_arbiter_config()
221 REG_WR_INT_VECT(marb_foo, regi_marb_foo, in crisv32_arbiter_config()
224 REG_WR_INT_VECT(marb_bar, regi_marb_bar, in crisv32_arbiter_config()
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
Darbiter.c153 REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, in crisv32_arbiter_config()
156 REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, in crisv32_arbiter_config()