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Searched refs:REG_GET (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/video/fbdev/omap2/dss/
Dhdmi4_core.c55 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
127 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
132 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
141 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
148 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
156 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
Dhdmi.h271 #define REG_GET(base, idx, start, end) \ macro
278 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
Ddsi.c120 #define REG_GET(dsidev, idx, start, end) \ macro
511 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
518 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1795 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2291 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2302 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2325 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2352 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2371 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2526 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
[all …]
Ddispc.c58 #define REG_GET(idx, start, end) \ macro
261 return REG_GET(rfld.reg, rfld.high, rfld.low); in mgr_fld_read()
581 return REG_GET(DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
589 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
594 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
1148 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); in dispc_init_fifos()
1228 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1230 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
2754 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); in dispc_ovl_enabled()
3611 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
[all …]
Dhdmi5.c337 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); in read_edid()
611 hd->wp_idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); in hdmi_audio_start()
Dhdmi_wp.c72 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
Ddss.c64 #define REG_GET(idx, start, end) \ macro
650 return REG_GET(DSS_CONTROL, 15, 15); in dss_get_hdmi_venc_clk_source()
Dhdmi5_core.c171 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); in hdmi_core_ddc_edid()
191 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); in hdmi_core_ddc_edid()
/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon.h2545 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro