Searched refs:REG_AXXX_CP_ME_CNTL (Results 1 – 2 of 2) sorted by relevance
289 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); in a3xx_hw_init()426 REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
299 #define REG_AXXX_CP_ME_CNTL 0x000001f6 macro