Searched refs:RD_REG_WORD (Results 1 – 14 of 14) sorted by relevance
29 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()32 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()37 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()44 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()62 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_unlock_nvram_access()77 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()81 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()84 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()[all …]
163 mb0 = RD_REG_WORD(®->mailbox0); in qla27xx_dump_mpi_ram()164 mb1 = RD_REG_WORD(®->mailbox1); in qla27xx_dump_mpi_ram()241 mb0 = RD_REG_WORD(®->mailbox0); in qla24xx_dump_ram()361 for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && in qla24xx_soft_reset()424 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()434 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()440 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()465 *buf++ = htons(RD_REG_WORD(dmp_reg++)); in qla2xxx_read_window()718 fw->hccr = htons(RD_REG_WORD(®->hccr)); in qla2300_fw_dump()724 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && in qla2300_fw_dump()[all …]
58 hccr = RD_REG_WORD(®->hccr); in qla2100_intr_handler()71 RD_REG_WORD(®->hccr); in qla2100_intr_handler()76 } else if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0) in qla2100_intr_handler()79 if (RD_REG_WORD(®->semaphore) & BIT_0) { in qla2100_intr_handler()81 RD_REG_WORD(®->hccr); in qla2100_intr_handler()101 RD_REG_WORD(®->semaphore); in qla2100_intr_handler()106 RD_REG_WORD(®->hccr); in qla2100_intr_handler()185 hccr = RD_REG_WORD(®->hccr); in qla2300_intr_handler()202 RD_REG_WORD(®->hccr); in qla2300_intr_handler()289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla2x00_mbx_completion()[all …]
48 first = RD_REG_WORD(addr); in qla2x00_debounce_register()51 second = RD_REG_WORD(addr); in qla2x00_debounce_register()
764 ha->pci_attr = RD_REG_WORD(®->ctrl_status); in qla2100_pci_config()808 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()816 RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()826 RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()831 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()846 ha->pci_attr = RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()996 if ((RD_REG_WORD(®->hccr) & in qla2x00_reset_chip()1002 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()1008 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_reset_chip()1012 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ in qla2x00_reset_chip()[all …]
1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla82xx_mbx_completion()2072 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_intr_handler()2073 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_intr_handler()2074 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_intr_handler()2141 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_msix_default()2142 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_msix_default()2143 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_msix_default()2236 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_poll()2237 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_poll()2238 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_poll()
2842 ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1); in qlafx00_async_event()2843 ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2); in qlafx00_async_event()2844 ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3); in qlafx00_async_event()2845 ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4); in qlafx00_async_event()2846 ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5); in qlafx00_async_event()2847 ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6); in qlafx00_async_event()2848 ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7); in qlafx00_async_event()2936 mb[0] = RD_REG_WORD(®->mailbox16); in qlafx00_intr_handler()2942 ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); in qlafx00_intr_handler()
110 #define RD_REG_WORD(addr) readw(addr) macro693 RD_REG_WORD(MAILBOX_REG(ha, reg, num))702 RD_REG_WORD(FB_CMD_REG(ha, reg))
156 value = RD_REG_WORD((__iomem void *)window); in qla27xx_read16()
3956 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla8044_intr_handler()3957 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla8044_intr_handler()3958 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla8044_intr_handler()
271 mb0 = RD_REG_WORD(®->isp24.mailbox0); in qla2x00_mailbox_command()275 ictrl = RD_REG_WORD(®->isp.ictrl); in qla2x00_mailbox_command()392 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); in qla2x00_mailbox_command()4653 mb0 = RD_REG_WORD(®->mailbox0); in qla81xx_write_mpi_register()
1464 RD_REG_WORD(®->ictrl); in qla2x00_enable_intrs()1479 RD_REG_WORD(®->ictrl); in qla2x00_disable_intrs()
767 ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); in qla1280_mailbox_timeout()770 RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); in qla1280_mailbox_timeout()868 RD_REG_WORD(&ha->iobase->istatus)); in qla1280_error_action()871 RD_REG_WORD(&ha->iobase->host_cmd), in qla1280_error_action()872 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()1091 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()1099 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()1470 RD_REG_WORD(®->host_cmd); in qla1280_initialize_adapter()1619 data = RD_REG_WORD(®->ictrl); in qla1280_chip_diag()1635 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_chip_diag()[all …]
60 #define RD_REG_WORD(addr) readw_relaxed(addr) macro64 #define RD_REG_WORD(addr) inw((unsigned long)addr) macro65 #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr)