Home
last modified time | relevance | path

Searched refs:RADEON_CLOCK_CNTL_INDEX (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_legacy_crtc.c937 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
958 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
Dradeon_cp.c287 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); in RADEON_READ_PLL()
693 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); in radeon_do_engine_reset()
728 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); in radeon_do_engine_reset()
Dr100.c2874 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2876 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); in r100_pll_errata_after_data()
2878 WREG32(RADEON_CLOCK_CNTL_INDEX, save); in r100_pll_errata_after_data()
2888 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2901 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
Dradeon_drv.h525 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
1863 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
Dradeon_legacy_tv.c286 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
Dradeon_legacy_encoders.c238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); in radeon_legacy_lvds_mode_set()
Dradeon_reg.h346 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
Dradeon_combios.c1147 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()