Searched refs:R128_WRITE (Results 1 - 4 of 4) sorted by relevance
/linux-4.1.27/drivers/gpu/drm/r128/ |
H A D | r128_irq.c | 57 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); r128_driver_irq_handler() 74 R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); r128_enable_vblank() 87 * R128_WRITE(R128_GEN_INT_CNTL, r128_disable_vblank() 97 R128_WRITE(R128_GEN_INT_CNTL, 0); r128_driver_irq_preinstall() 99 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); r128_driver_irq_preinstall() 114 R128_WRITE(R128_GEN_INT_CNTL, 0); r128_driver_irq_uninstall()
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H A D | r128_cce.c | 83 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp); r128_do_pixcache_flush() 174 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); r128_cce_load_microcode() 176 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_load_microcode() 178 R128_WRITE(R128_PM4_MICROCODE_DATAL, r128_cce_load_microcode() 196 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp); r128_do_cce_flush() 231 R128_WRITE(R128_PM4_BUFFER_CNTL, r128_do_cce_start() 235 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); r128_do_cce_start() 246 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); r128_do_cce_reset() 247 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); r128_do_cce_reset() 257 R128_WRITE(R128_PM4_MICRO_CNTL, 0); r128_do_cce_stop() 258 R128_WRITE(R128_PM4_BUFFER_CNTL, r128_do_cce_stop() 282 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); r128_do_engine_reset() 284 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); r128_do_engine_reset() 288 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index); r128_do_engine_reset() 289 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl); r128_do_engine_reset() 322 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET); r128_cce_init_ring_buffer() 324 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); r128_cce_init_ring_buffer() 325 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); r128_cce_init_ring_buffer() 328 R128_WRITE(R128_PM4_BUFFER_WM_CNTL, r128_cce_init_ring_buffer() 339 R128_WRITE(R128_BUS_CNTL, tmp); r128_cce_init_ring_buffer() 550 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); r128_do_init_cce() 553 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); r128_do_init_cce() 570 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); r128_do_init_cce()
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H A D | r128_drv.h | 397 #define R128_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val)) macro 405 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 521 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail); \
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H A D | r128_state.c | 1243 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); r128_do_init_pageflip() 1244 R128_WRITE(R128_CRTC_OFFSET_CNTL, r128_do_init_pageflip() 1259 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); r128_do_cleanup_pageflip() 1260 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); r128_do_cleanup_pageflip()
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