| /linux-4.1.27/arch/sh/boards/mach-highlander/ |
| H A D | irq-r7780rp.c | 23 PSW, /* Push Switch */ enumerator in enum:__anon2553
38 INTC_IRQ(PSW, IRQ_PSW),
45 0, 0, 0, 0, 0, 0, PSW, AX88796 } },
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| H A D | irq-r7780mp.c | 28 PSW, /* Push Switch */ enumerator in enum:__anon2552
42 INTC_IRQ(PSW, IRQ_PSW),
52 0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },
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| /linux-4.1.27/arch/parisc/include/uapi/asm/ |
| H A D | sigcontext.h | 12 unsigned long sc_gr[32]; /* PSW in sc_gr[0] */
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| H A D | ptrace.h | 19 unsigned long gr[32]; /* PSW is in gr[0] */
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| /linux-4.1.27/arch/s390/kernel/ |
| H A D | base.S | 90 larl %r4,.Lcontinue_psw # Save PSW flags
93 larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
95 lg %r4,0(%r4) # Save PSW
109 larl %r4,.Lcontinue_psw # Restore PSW flags
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| H A D | runtime_instr.c | 33 * Make sure the RI bit is deleted from the PSW. If the user did not disable_runtime_instr()
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| H A D | sclp.S | 88 .long 0, 0, 0, 0 # old ext int PSW
90 .long 0x00080000, 0x80000000+.LwaitS1 # PSW to handle ext int
92 .quad 0, .LwaitS1 # PSW to handle ext int, 64 bit
94 .long 0x010a0000, 0x00000000+.LloopS1 # PSW to wait for ext int
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| H A D | head.S | 10 * 1) load the image directly into ram at address 0 and do an PSW restart
38 .long 0x02000068,0x60000050 # (a PSW and two CCWs).
48 .long 0x02000370,0x60000050 # the channel program the PSW
338 # this is called either by the ipl loader or directly by PSW restart
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| H A D | dumpstack.c | 135 printk("%s PSW : %p %p", mode, (void *)regs->psw.mask, (void *)regs->psw.addr); show_registers()
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| H A D | entry.S | 409 tmhh %r8,0x4000 # PER bit set in old PSW ?
675 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
753 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
771 # PSW restart interrupt handler
1017 # will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other
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| H A D | nmi.c | 215 /* Check if old PSW is valid */ s390_revalidate_registers()
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| H A D | setup.c | 352 * Set up PSW restart to call ipl.c:do_restart(). Copy the relevant setup_lowcore()
354 * PSW restart is done on an offline CPU that has lowcore zero. setup_lowcore()
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| H A D | swsusp.S | 202 larl %r4,.Lrestart_suspend_psw /* Set new restart PSW */
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| H A D | signal.c | 141 /* Copy a 'clean' PSW mask to the user to avoid leaking save_sigregs()
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| H A D | dis.c | 1980 printk("%s Code: Bad PSW.\n", mode); show_code()
1991 /* Looks good, sequence ends at PSW. */ show_code()
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| H A D | smp.c | 280 * Call function via PSW restart on pcpu and stop the current cpu.
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| H A D | ptrace.c | 102 /* Take care of the PER enablement bit in the PSW. */ update_cr_regs()
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| /linux-4.1.27/arch/m32r/include/asm/ |
| H A D | m32r.h | 119 * PSW (Processor Status Word)
122 /* PSW bit */
132 /* PSW bit map */
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| H A D | processor.h | 104 /* User process Backup PSW */
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| /linux-4.1.27/drivers/s390/char/ |
| H A D | sclp_quiesce.c | 25 /* Shutdown handler. Signal completion of shutdown by loading special PSW. */ do_machine_quiesce()
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| /linux-4.1.27/arch/s390/include/asm/ |
| H A D | cpu_mf.h | 107 unsigned int T:1; /* 26 PSW DAT mode */
108 unsigned int W:1; /* 27 PSW wait state */
109 unsigned int P:1; /* 28 PSW Problem state */
110 unsigned int AS:2; /* 29-30 PSW address-space control */
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| H A D | processor.h | 207 * Set PSW to specified value.
215 * Set PSW mask to specified value, while leaving the
216 * PSW addr pointing to the next instruction.
234 * Rewind PSW instruction address by specified number of bytes.
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| H A D | ptrace.h | 32 unsigned long long key : 4; /* PSW Key */
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| /linux-4.1.27/arch/parisc/kernel/ |
| H A D | hpmc.S | 113 * Do this before turning the PSW M bit off.
134 ldo 8(%r0),%r4 /* PSW Q on, PSW M off */
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| H A D | ptrace.c | 30 /* PSW bits we allow the debugger to modify */
93 * disable interrupts in the tasks PSW here also, to avoid user_enable_single_step()
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| H A D | syscall.S | 158 PSW value is stored. This is needed for gdb and sys_ptrace. */
265 * are. This saves only the lower 8 bits of PSW, so that the C
269 * restore. An interrupt results in a full PSW saved with the
271 * in the saved PSW.
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| H A D | head.S | 262 rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */
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| H A D | entry.S | 829 * context via sigcontext. Also Filter the PSW for the same reason.
1882 /* We have to return via an RFI, so that PSW T and R bits can be set
1890 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1891 ldi 0x0b,%r20 /* Create new PSW */
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| H A D | pacache.S | 184 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
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| /linux-4.1.27/arch/s390/kvm/ |
| H A D | gaccess.h | 48 * applying the rules of the vcpu's addressing mode defined by PSW bits 31
178 * In order to copy data to guest space the PSW of the vcpu is inspected:
181 * the address space bits of the PSW:
183 * The addressing mode of the PSW is also inspected, so that address wrap
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| H A D | intercept.c | 263 * the new PSW does not have external interrupts disabled. In the first case,
279 /* We can not handle clock comparator or timer interrupt with bad PSW */ handle_external_interrupt()
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| H A D | kvm-s390.c | 1922 * by a DAT access exception, the PSW still points to the faulting vcpu_post_run_fault_in_sie()
1925 * to be able to forward the PSW. vcpu_post_run_fault_in_sie()
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| H A D | priv.c | 769 /* Rewind PSW to repeat the ESSA instruction */ handle_essa()
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| /linux-4.1.27/arch/parisc/include/asm/ |
| H A D | bitops.h | 128 * One side effect of "extr" instructions is it sets PSW[N] bit.
129 * How PSW[N] (nullify next insn) gets set is determined by the
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| H A D | compat.h | 116 compat_int_t sc_gr[32]; /* PSW in sc_gr[0] */
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| H A D | processor.h | 287 * Final Note: For entry from syscall, the W (wide) bit of the PSW
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| /linux-4.1.27/arch/m32r/kernel/ |
| H A D | head.S | 38 /* Initilalize PSW */
187 ;; clear PSW
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| H A D | entry.S | 103 #define PSW(reg) @(0x4C,reg) define
156 ld r4, PSW(sp)
183 ld r4, PSW(sp) ; interrupts off (exception path) ?
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| H A D | process.c | 78 printk("BPC[%08lx]:PSW[%08lx]:LR [%08lx]:FP [%08lx]\n", \ show_regs()
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| H A D | smp.c | 526 * PSW IE = 1; stop_this_cpu()
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| /linux-4.1.27/drivers/usb/host/ |
| H A D | ohci.h | 122 /* PSW is only for ISO. Only 1 PSW entry is used, but on
656 * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are
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| /linux-4.1.27/arch/parisc/mm/ |
| H A D | fault.c | 164 * iaoq[0]+4, and clear the B bit in the PSW fixup_exception()
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| /linux-4.1.27/arch/m32r/mm/ |
| H A D | fault.c | 86 * If BPSW IE bit enable --> set PSW IE bit do_page_fault()
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| /linux-4.1.27/drivers/usb/serial/ |
| H A D | keyspan_pda.c | 319 There is minimal hw support for parity (a PSW bit seems to hold the keyspan_pda_set_termios()
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| /linux-4.1.27/arch/s390/mm/ |
| H A D | fault.c | 530 * the PSW already points to the correct location. do_protection_exception()
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| /linux-4.1.27/arch/arm/kernel/ |
| H A D | signal.c | 520 * debugger will see the already changed PSW. do_signal()
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| /linux-4.1.27/drivers/tty/serial/ |
| H A D | 68328serial.c | 1202 PJSEL &= 0xCF; /* PSW enable second port output */ rs68328_init()
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