| /linux-4.1.27/arch/unicore32/include/asm/ |
| D | ptrace.h | 26 (!((regs)->UCreg_asr & PSR_I_BIT))
43 if ((regs->UCreg_asr & PSR_I_BIT) == 0) { in valid_user_regs()
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| D | irqflags.h | 19 #define ARCH_IRQ_DISABLED (PRIV_MODE | PSR_I_BIT)
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| D | assembler.h | 46 or \temp, \temp, #PSR_I_BIT | PRIV_MODE
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| /linux-4.1.27/arch/unicore32/kernel/ |
| D | setup.c | 124 "r" (PSR_R_BIT | PSR_I_BIT | INTR_MODE), in cpu_init()
126 "r" (PSR_R_BIT | PSR_I_BIT | ABRT_MODE), in cpu_init()
128 "r" (PSR_R_BIT | PSR_I_BIT | EXTN_MODE), in cpu_init()
130 "r" (PSR_R_BIT | PSR_I_BIT | PRIV_MODE) in cpu_init()
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| D | entry.S | 260 cand.a r3, #PSR_I_BIT
262 andn r17, r17, #PSR_I_BIT
330 cand.a r3, #PSR_I_BIT
332 andn r17, r17, #PSR_I_BIT
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| D | head.S | 64 or r0, #PSR_R_BIT | PSR_I_BIT @ disable irqs
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| /linux-4.1.27/arch/arm/kernel/ |
| D | fiqasm.S | 26 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
39 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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| D | entry-armv.S | 332 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
333 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
337 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
338 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
346 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
347 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
351 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
352 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
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| D | setup.c | 496 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), in cpu_init()
498 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), in cpu_init()
500 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), in cpu_init()
502 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), in cpu_init()
504 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) in cpu_init()
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| D | iwmmxt.S | 200 orr r2, ip, #PSR_I_BIT @ disable interrupts
252 orr r2, ip, #PSR_I_BIT @ disable interrupts
290 orr r2, ip, #PSR_I_BIT @ disable interrupts
357 orr ip, r2, #PSR_I_BIT @ disable interrupts
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| D | entry-header.S | 288 tst \rpsr, #PSR_I_BIT
290 tst \rpsr, #PSR_I_BIT
318 mov r1, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
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| D | head-nommu.S | 55 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
99 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
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| /linux-4.1.27/arch/arm/include/asm/ |
| D | ptrace.h | 42 (!((regs)->ARM_cpsr & PSR_I_BIT))
60 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { in valid_user_regs()
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| D | assembler.h | 103 msr cpsr_c, #PSR_I_BIT | SVC_MODE
175 tst \oldcpsr, #PSR_I_BIT
325 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
340 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
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| D | irqflags.h | 18 #define IRQMASK_I_BIT PSR_I_BIT
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| /linux-4.1.27/arch/arm64/include/asm/ |
| D | ptrace.h | 141 (!((regs)->pstate & PSR_I_BIT))
160 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { in valid_user_regs()
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| D | irqflags.h | 90 return flags & PSR_I_BIT; in arch_irqs_disabled_flags()
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| /linux-4.1.27/arch/arm/kvm/ |
| D | reset.c | 37 .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
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| D | emulate.c | 301 *vcpu_cpsr(vcpu) |= PSR_I_BIT; in kvm_inject_undefined()
336 *vcpu_cpsr(vcpu) |= PSR_I_BIT | PSR_A_BIT; in inject_abt()
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| /linux-4.1.27/arch/arm64/include/uapi/asm/ |
| D | ptrace.h | 44 #define PSR_I_BIT 0x00000080 macro
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| /linux-4.1.27/arch/arm/mach-s3c24xx/ |
| D | sleep.S | 56 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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| /linux-4.1.27/arch/arm64/kvm/ |
| D | reset.c | 37 .regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
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| D | inject_fault.c | 29 PSR_I_BIT | PSR_D_BIT)
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| D | hyp.S | 1104 mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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| /linux-4.1.27/arch/arm/mach-s3c64xx/ |
| D | sleep.S | 43 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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| /linux-4.1.27/arch/arm/mach-rockchip/ |
| D | sleep.S | 29 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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| /linux-4.1.27/arch/unicore32/include/uapi/asm/ |
| D | ptrace.h | 29 #define PSR_I_BIT 0x00000080 macro
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| /linux-4.1.27/arch/arm/include/uapi/asm/ |
| D | ptrace.h | 73 #define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */ macro
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| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| D | crunch-bits.S | 213 orr r2, ip, #PSR_I_BIT @ disable interrupts
259 orr r2, ip, #PSR_I_BIT @ disable interrupts
292 orr r2, ip, #PSR_I_BIT @ disable interrupts
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| /linux-4.1.27/arch/arm/mm/ |
| D | proc-feroceon.S | 263 orr r3, r2, #PSR_I_BIT
309 orr r3, r2, #PSR_I_BIT
341 orr r3, r2, #PSR_I_BIT
372 orr r3, r2, #PSR_I_BIT
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| D | proc-xsc3.S | 110 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
451 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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| D | proc-xscale.S | 147 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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| /linux-4.1.27/arch/unicore32/mm/ |
| D | proc-ucv2.S | 23 mov ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE
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| /linux-4.1.27/arch/arm/probes/kprobes/ |
| D | core.c | 508 cpsr = regs->ARM_cpsr | PSR_I_BIT; in setjmp_pre_handler()
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| D | test-core.c | 1200 regs->ARM_cpsr |= PSR_I_BIT; in setup_test_context()
1288 regs->ARM_cpsr &= ~PSR_I_BIT; in test_after_pre_handler()
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| /linux-4.1.27/arch/arm64/kernel/ |
| D | head.S | 587 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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