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Searched refs:PLLE_SS_CNTL_INTERP_RESET (Results 1 – 1 of 1) sorted by relevance

/linux-4.1.27/drivers/clk/tegra/
Dclk-pll.c81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) macro
85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
1346 val &= ~PLLE_SS_CNTL_INTERP_RESET; in clk_plle_tegra114_enable()