| /linux-4.1.27/include/linux/iio/frequency/ |
| H A D | ad9523.h | 127 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
128 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
129 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
130 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
131 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
134 * @rpole2: PLL2 loop filter Rpole resistor value.
135 * @rzero: PLL2 loop filter Rzero resistor value.
136 * @cpole1: PLL2 loop filter Cpole capacitor value.
137 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
173 /* PLL2 Setting */
182 /* Loop Filter PLL2 */
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| /linux-4.1.27/sound/soc/codecs/ |
| H A D | ak4642.c | 116 #define PLL2 (1 << 6) macro
119 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
349 pll = PLL2; ak4642_dai_set_sysclk()
352 pll = PLL2 | PLL0; ak4642_dai_set_sysclk()
355 pll = PLL2 | PLL1; ak4642_dai_set_sysclk()
358 pll = PLL2 | PLL1 | PLL0; ak4642_dai_set_sysclk()
361 pll = PLL3 | PLL2; ak4642_dai_set_sysclk()
364 pll = PLL3 | PLL2 | PLL0; ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1; ak4642_dai_set_sysclk()
375 pll = PLL3 | PLL2 | PLL1 | PLL0; ak4642_dai_set_sysclk()
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| H A D | adav80x.c | 208 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
224 clk = "PLL2"; adav80x_dapm_sysclk_check()
271 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
274 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
610 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2"); adav80x_set_sysclk()
612 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2"); adav80x_set_sysclk()
808 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2"); adav80x_probe()
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| H A D | wm8804.c | 41 { 4, 0xFD }, /* R4 - PLL2 */
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| H A D | adau1373.c | 795 SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
984 { "SYSCLK2", NULL, "PLL2" },
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| H A D | alc5632.c | 66 { 70, 0x0000 }, /* R70 - PLL2 Control */
756 /* enable PLL2 */ alc5632_set_dai_pll()
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| H A D | wm8990.h | 811 * R61 (0x3D) - PLL2
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| H A D | wm8991.h | 800 * R61 (0x3D) - PLL2
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| H A D | wm8990.c | 110 { 61, 0x0031 }, /* R61 - PLL2 */
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| H A D | wm8991.c | 100 { 61, 0x0031 }, /* R61 - PLL2 */
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| H A D | rt5677.c | 2503 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
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| H A D | wm8962.h | 2572 * R129 (0x81) - PLL2
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| /linux-4.1.27/include/linux/mfd/ |
| H A D | tc6393xb.h | 24 u16 scr_pll2cr; /* PLL2 Control */
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| /linux-4.1.27/drivers/media/i2c/ |
| H A D | saa711x_regs.h | 189 /* second PLL (PLL2) and Pulsegenerator Programming */
543 /* second PLL (PLL2) and Pulsegenerator Programming */
549 "Nominal PLL2 DTO"},
551 "PLL2 Increment"},
553 "PLL2 Status"},
566 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
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| H A D | saa7115.c | 629 /* PLL2 lock detection settings: 71 lines 50% phase error */
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| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 135 #define PLL2 118 macro
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| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 135 #define PLL2 118 macro
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| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 135 #define PLL2 118 macro
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| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 135 #define PLL2 118 macro
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| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 135 #define PLL2 118 macro
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| /linux-4.1.27/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 135 #define PLL2 118 macro
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| /linux-4.1.27/drivers/clk/shmobile/ |
| H A D | clk-sh73a0.c | 115 /* handle CFG bit for PLL1 and PLL2 */ sh73a0_cpg_register_clock()
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| /linux-4.1.27/drivers/video/fbdev/aty/ |
| H A D | radeonfb.h | 240 /* Computed values for PLL2 */
245 /* PLL2 registers */
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| /linux-4.1.27/drivers/media/dvb-frontends/ |
| H A D | zl10039.c | 55 PLL2, enumerator in enum:zl10039_reg_addr
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| H A D | tda10023.c | 242 /* PLL2 */ tda10023_init()
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| /linux-4.1.27/arch/arm/mach-shmobile/ |
| H A D | clock-sh73a0.c | 93 /* PLL0, PLL1, PLL2, PLL3 */ pll_recalc()
100 /* handle CFG bit for PLL1 and PLL2 */ pll_recalc()
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| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| H A D | clock.c | 554 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", ep93xx_clock_init()
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| /linux-4.1.27/drivers/iio/frequency/ |
| H A D | ad9523.c | 827 * PLL2 Setup ad9523_setup()
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| /linux-4.1.27/drivers/mfd/ |
| H A D | tc6393xb.c | 48 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
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| H A D | sm501.c | 167 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", sm501_dump_clk()
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| /linux-4.1.27/drivers/clk/sirf/ |
| H A D | clk-common.c | 25 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
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| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | clk-imx51-imx53.c | 295 /* Set SDHC parents to be PLL2 */ mx5_clocks_common_init()
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| /linux-4.1.27/drivers/clk/qcom/ |
| H A D | mmcc-msm8960.c | 2369 [PLL2] = &pll2.clkr,
2529 [PLL2] = &pll2.clkr,
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| /linux-4.1.27/sound/pci/hda/ |
| H A D | patch_realtek.c | 2999 alc5505_coef_set(codec, 0x61b4, 0x040a2b03); /* Stop PLL2 */ alc5505_dsp_halt()
3024 alc5505_coef_set(codec, 0x61b4, 0x04132b00); /* PLL2 control */ alc5505_dsp_init()
3044 alc5505_coef_set(codec, 0x61b4, 0x040e2b02); /* PLL2 control */ alc5505_dsp_init()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | init.c | 977 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); init_pll2()
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