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Searched refs:PIPE_B (Results 1 – 17 of 17) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_runtime_pm.c199 1 << PIPE_C | 1 << PIPE_B); in hsw_power_well_post_enable()
223 1 << PIPE_C | 1 << PIPE_B); in skl_power_well_post_enable()
602 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | in vlv_dpio_cmn_power_well_enable()
653 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | in chv_dpio_cmn_power_well_enable()
655 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | in chv_dpio_cmn_power_well_enable()
684 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
769 power_well->data != PIPE_B && in chv_pipe_power_well_enable()
796 power_well->data != PIPE_B && in chv_pipe_power_well_disable()
1172 .data = PIPE_B,
Dintel_pm.c372 case PIPE_B: in vlv_get_fifo_size()
858 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | in vlv_write_wm_values()
859 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | in vlv_write_wm_values()
870 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
871 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
883 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
884 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
885 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | in vlv_write_wm_values()
891 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
[all …]
Dintel_panel.c525 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
612 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_set_backlight()
735 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_disable_backlight()
934 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_enable_backlight()
1288 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
Dintel_dsi.c609 dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & in intel_dsi_get_hw_state()
614 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1043 intel_encoder->crtc_mask = (1 << PIPE_B); in intel_dsi_init()
Di915_irq.c486 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1698 case PIPE_B: in valleyview_pipestat_irq_handler()
3113 if (pipe_mask & 1 << PIPE_B) in gen8_irq_power_well_post_enable()
3114 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, in gen8_irq_power_well_post_enable()
3115 dev_priv->de_irq_mask[PIPE_B], in gen8_irq_power_well_post_enable()
3116 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); in gen8_irq_power_well_post_enable()
3459 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3607 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3789 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3992 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
Dintel_hdmi.c1374 if (pipe != PIPE_B) { in chv_hdmi_pre_pll_enable()
1395 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1403 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1415 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
Dintel_dp.c352 else if (pipe == PIPE_B) in vlv_power_sequencer_kick()
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_power_sequencer_pipe()
476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
2582 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_steal_power_sequencer()
2784 if (pipe != PIPE_B) { in chv_dp_pre_pll_enable()
2805 if (pipe != PIPE_B) in chv_dp_pre_pll_enable()
2813 if (pipe != PIPE_B) in chv_dp_pre_pll_enable()
2825 if (pipe != PIPE_B) in chv_dp_pre_pll_enable()
5433 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
5436 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
Dintel_display.c1252 panel_pipe = PIPE_B; in assert_panel_unlocked()
1261 panel_pipe = PIPE_B; in assert_panel_unlocked()
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in assert_pipe()
1751 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll()
1752 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1759 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_disable_pll()
1780 if (pipe == PIPE_B) in vlv_disable_pll()
1810 if (pipe != PIPE_B) { in chv_disable_pll()
2128 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); in intel_enable_pipe()
2176 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in intel_disable_pipe()
[all …]
Dintel_ddi.c1335 case PIPE_B: in intel_ddi_enable_transcoder_func()
1471 *pipe = PIPE_B; in intel_ddi_get_hw_state()
Di915_cmd_parser.c454 GEN7_PIPE_DE_LOAD_SL(PIPE_B),
Dintel_drv.h712 case PIPE_B: in vlv_pipe_to_channel()
Dintel_sprite.c462 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) in vlv_update_plane()
Di915_debugfs.c3161 .pipe = PIPE_B,
3352 case PIPE_B: in vlv_pipe_crc_ctl_reg()
3453 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Di915_drv.h111 PIPE_B, enumerator
Di915_reg.h33 (pipe) == PIPE_B ? (b) : (c))
/linux-4.1.27/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro
Dintelfbhw.c1062 if (pipe == PIPE_B) { in intelfbhw_mode_to_hw()
1305 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()